An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Power semiconductor device

Semiconductor Power Devices

Recent growth of the insulated gate bipolar transistor (IGBT) module market has been driven largely by the increasing demand for an efficient way to control and distribute power in the field of renewable energy, hybrid/electric vehicles, and industrial equipment. For safety-critical and mission-critical applications, the reliability of IGBT modules is still a concern. Understanding the physics-of-failure of IGBT modules has been critical to the development of effective condition monitoring (CM) techniques as well as reliable prognostic methods. This review paper attempts to summarize past developments and recent advances in the area of CM and prognostics for IGBT modules. The improvement in material, fabrication, and structure is described. The CM techniques and prognostic methods proposed in the literature are presented. This paper concludes with recommendations for future research topics in the CM and prognostics areas.

Physics-of-Failure, Condition Monitoring, and Prognostics of Insulated Gate Bipolar Transistor Modules: A Review

An avalanche generation phenomenon has a large influence on turn-off switching loss and reverse-biased safe operating area of high-voltage insulated gate bipolar transistors (IGBTs). The purpose of this paper is to clarify the correlation between the avalanche multiplication phenomenon and the turn-off characteristics. We introduce a turn-off switching analytical model of IGBTs that considers the avalanche multiplication effect. It is concluded that the criterion of dynamic avalanche depends on the gate resistance. In the case of 4.5-kV IGBTs, the gate resistance of more than 200 /spl Omega//spl middot/cm/sup 2/ is needed to suppress the dynamic avalanche generation under a clumped inductive load circuit. On the contrary, the turn-off switching loss increases in the case that the gate resistance R/sub G/ is increased to more than approximately 100 /spl Omega//spl middot/cm/sup 2/. Theses results show that to realize low turn-off switching loss, it is necessary to ensure that the gate resistance is below a constant value, such as 100 /spl Omega//spl middot/cm/sup 2/. However, at high current density, such as 80 A/cm/sup 2/, the dynamic avalanche will generate under such small gate resistance condition. Therefore, it is important to develop IGBTs without destruction even under the condition of dynamic avalanche generation.

Turn-off switching analysis considering dynamic avalanche effect for low turn-off loss high-voltage IGBTs

Disclosed is a semiconductor device capable of stabilizing a gate voltage at high voltage and high current, protecting the device from breakdown by preventing current nonuniformity and oscillations and the like, thereby improving reliability, and a method for controlling the semiconductor device. The semiconductor device comprises an n-type base layer, a p-type emitter layer, which is formed on a surface of the n-type base layer, a collector electrode, formed on a surface of the p-type emitter layer, a p-type base layer, formed on a surface on the n-type base layer which is opposite to the p-type emitter layer, an n-type source layer, formed in a surface of the p-type base layer, an emitter electrode, formed on the n-type source layer and the p-type base layer, and a gate electrode, contacting the n-type source layer, the p-type base layer and the n-type base layer, with a gate insulating film interposed therebetween, wherein when a voltage is applied between the collector electrode and the emitter electrode, the capacitance of the gate electrode is always a positive value or zero.

Semiconductor device and control method thereof

An IGBT has a p-emitter layer and p-base layer, which are arranged on both sides of an n-base layer. A pair of main trenches are formed to extend through the p-base layer and reach the n-base layer. In a current path region interposed between the main trenches, a pair of n-emitter layers are formed on the surface of the p-base layer. A narrowing trench is formed to extend through the p-base layer and reach the n-base layer. The narrowing trench narrows a hole flow path formed from the n-base layer to the emitter electrode through the p-base layer, thereby increasing the hole current resistance.

Semiconductor device with trench gate having structure to promote conductivity modulation

In this paper, we propose a new collector design concept for high voltage IGBTs/IEGTs, which is composed of a low injection efficiency p-emitter and low transport factor n-buffer. The n-buffer with low transport factor provides decreasing hole injection from p-emitter to n-base to improve the trade-off relation between collector-emitter saturation voltage and turn-off loss. Besides, the n-buffer with low transport factor does not prevent hole injection from p-emitter to n-base at the device turn-on period. As the low transport n-buffer is combined with a low efficiency p-emitter, total switching loss including turn-off loss and turn-on loss decreases. The new collector design concept was applied to 4.5 kV IEGTs, and the fabricated device has demonstrated a reduction of total switching loss by 11% compared with that of the device having only low injection efficiency p-emitter. The fabricated device with the new collector design concept also has excellent turn-off capability.

Hideaki Ninomiya

Papers

Power semiconductor device

Turn-off switching analysis considering dynamic avalanche effect for low turn-off loss high-voltage IGBTs

Semiconductor device and control method thereof

Semiconductor device with trench gate having structure to promote conductivity modulation

New collector design concept for 4.5 kV injection enhanced gate transistor (IEGT)