Proceedings ArticleDOI
Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA
Shouqian Yu,Lili Yi,Weihai Chen,Zhaojin Wen +3 more
- pp 2633-2638
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TLDR
A multi-channel UART controller based on FIFO (first in first out) technique and FPGA (field programmable gate array) to implement communication in modern complex control systems quickly and effectively is presented.Abstract:
To meet modern complex control systems communication demands, the paper presents a multi-channel UART controller based on FIFO (first in first out) technique and FPGA (field programmable gate array). The paper presents design method of asynchronous FIFO and structure of the controller. This controller is designed with FIFO circuit block and UART (universal asynchronous receiver transmitter) circuit block within FPGA to implement communication in modern complex control systems quickly and effectively. Form the communication sequence diagrams, it is easily to know that this controller can be used to implement communication when master equipment and slaver equipment are set at different Baud Rate. It also can be used to reduce synchronization error between sub-systems in a system with several sub-systems. The controller is reconfigurable and scalable.read more
Citations
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Proceedings ArticleDOI
A low power UART design based on asynchronous techniques
TL;DR: This work investigates whether this simple clocked hardware protocol can be advantageously implemented using asynchronous design techniques, and implements and compared a full duplex clocked and asynchronous UART.
Proceedings ArticleDOI
An FPGA implementation of shift converter block technique on FIFO for RS232 to universal serial bus converter
TL;DR: To meet the standard modern system communication demands, the paper represents the implementation of bidirectional shift converter technique for the embedded converter RS232 to Universal Serial Bus circuit block within FPGA using Verilog HDL language to be applied in a system wireless communication within Zigbee protocol.
Proceedings ArticleDOI
An FPGA implementation of shift converter block technique on FIFO for UART
TL;DR: To meet the standard modern system wireless communication demands, the paper represents the implementation of bidirectional shift converter technique with FIFO circuit block and UART circuit block through FPGA device using Verilog HDL language to be applied in embedded system converter RS232 to USB (Universal Serial Bus).
Proceedings ArticleDOI
High-Speed and Real-Time Communication Controller for Embedded Integrated Navigation System
Zhang Guo-long,Xu Xiaosu +1 more
TL;DR: To meet the complex requirements of the miniature embedded integrated (INS/GPS) navigation system based on DSP, all peripheral circuits were integrated in single chip of FPGA, such as logic control module, serial/parallel data conversion and FIFO, etc.
Proceedings ArticleDOI
Study on the communication between FPGA and observer using Controller Area Network and UART
Yu Zhu,Yingnan Wang,Uwe Schaefer +2 more
TL;DR: The two protocols: Controller Area Network (CAN) and Universal Asynchronous Receiver and Transmitter (UART) are studied and how to design a non data loss communication system working at the highest transmission rate is described.
References
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Book
Control Systems Theory with Engineering Applications
TL;DR: Preface Acknowledgments Introduction: Modeling, Identification, Optimization, and Control Mathematical Model Developments Modeling of Dynamic Systems using Matlab and SIMULINK Analysis and Control of Linear Dynamic Systems Analysis, identification, and control of Nonlinear Dynamic Systems.
Journal Article
UART-based Reliable Communication and Performance Analysis
TL;DR: To establish a reliable UART-based bus network, some connection proposals are presented and analyzed and it is shown that the baudrate-recalibrated time is determined by two aspects that are the inter-slot condition and the intra- slot condition.
Journal Article
Implementation of Parallel Signal Processing System Based on FPGA and Multi-DSP
TL;DR: The paper presents a parallel processing system based on 4 chips of TMS320C6701——high performance floating-point DSP of TI that accomplishes the communication between DSPs through the software-FIFO architecture in FPGA.