VLSI circuits challenge traditional electronic packaging methods. Several new package types, however, efficiently handle high-I/O devices.

The thermal failure of electronic systems is becoming an increasingly difficult design problem, because of the trend to increase the packing density of components. This paper describes research in which the finite-element method (FEM) is used to investigate steady-state heat transfer in dual-in-line microelectronic package (DIP). Although the paper provides data for the specialist in package design, background information on heat transfer and the FEM has been included to demonstrate the broad applicability of the methods used. The stages in the development of finite-element models of first an 8-pin, and then a 16-pin, DIP are described. A systematic thermal analysis was carried out on the finite-element model of 16-pin DIP when cooled by air, first by natural and then by forced convection. The FEM revealed the complex 3-dimensional temperature field within the package. Computer runs over a range of power dissipation rates showed how both temperature distribution, and thermal resistance, changed in response to changes in external convection. As well as providing data for package cooling, the research highlights the difficulties inherent in providing a standard definition of thermal resistance for users.

Large-Scale Cost-Effective Packaging

Citations

Thermal analysis of a dual-in-line package using the finite-element method

VLSI implementation of control section of overlapped 3-bit scanning 64-bit multiplier

References

Thermal analysis of a dual-in-line package using the finite-element method

VLSI implementation of control section of overlapped 3-bit scanning 64-bit multiplier

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