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Media processor hardware/software co-simulation andco-verification platform

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TLDR
A general heterogeneous hardware/ software co-simulation and co-verification platform was constructed based on the hardware/software co-design method, and the experimental results show that the media processor designed and simulated based on this platform are accelerated 7~15 ten thousand times compared with hardware description language(HDL) software simulator.
Abstract
To accelerate media processor's hardware/software co-simulation process, a general heterogeneous hardware/software co-simulation and co-verification platform was constructed based on the hardware/software co-design method. For validating of the media processor design, the configurable and reusable platform consists of hardware sub-platform and software sub-platform. Using this platform, the designed 32-bit media digital signal processor MediaDSP3200 series were verified, and application programs were developed. The experimental results show that the media processor designed and simulated based on this platform are accelerated 7~15 ten thousand times compared with hardware description language(HDL) software simulator. The co-simulation and co-verification platform has satisfied feature by using the software sub-platform controller, the hardware sub-platform can provide some debug functions that are seldom implemented in hardware simulator.

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Citations
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Proceedings ArticleDOI

System-on-chip architecture with media DSP and RISC core for media application

TL;DR: The MediaSoC322xA consists of two fully programmable processor cores and integrates digital video encoder that combines RISC/DSP oriented functions and multimedia processing, and the RISC3200 for bit stream processing and control function.
Proceedings ArticleDOI

A Novel Component-based Hardware-Software Co-simulation System Based on OR1200

TL;DR: A component model for trustworthy systems which unifies the concepts of hardware components and software components is defined and it uses an instruction set simulator (ISS) instead of OR1200 CPU when simulating the SoC system.
References
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Proceedings ArticleDOI

System-on-chip architecture with media DSP and RISC core for media application

TL;DR: The MediaSoC322xA consists of two fully programmable processor cores and integrates digital video encoder that combines RISC/DSP oriented functions and multimedia processing, and the RISC3200 for bit stream processing and control function.
Proceedings ArticleDOI

A Novel Component-based Hardware-Software Co-simulation System Based on OR1200

TL;DR: A component model for trustworthy systems which unifies the concepts of hardware components and software components is defined and it uses an instruction set simulator (ISS) instead of OR1200 CPU when simulating the SoC system.
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