Patent
Memory with reconfiguration to avoid uncorrectable errors
TLDR
In this paper, a memory having circuits for correcting single errors in a word read from the memory is provided with means to reconfigure the memory so that a configuration having a double, uncorrectable, error is changed to a configuration with two single, correctable errors.Abstract:
A memory having circuits for correcting single errors in a word read from the memory is provided with means to reconfigure the memory so that a configuration having a double, uncorrectable, error is changed to a configuration having two single, correctable errors. In one embodiment, interchanging plug-in components for two or more bit positions produces a new configuration; in another embodiment, the wiring to the plug-in components is easily changeable.read more
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Patent
System for updating error map of fault tolerant memory
TL;DR: In this article, an online system for mapping errors into an error map is described, where read data is transferred between a relatively large fault tolerant semiconductor memory system and a CPU without interfering with the normal use of the memory.
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Semiconductor memory with an improved dummy cell arrangement and with a built-in error correcting code circuit
Takashi Shinoda,Osamu Sakai +1 more
TL;DR: In this article, a dummy cell arrangement is provided wherein each dummy cell includes at least two series-connected semiconductor elements to provide a predetermined dummy cell conductance to establish a reference value.
Patent
Solid state memory array using address block bit substitution to compensate for non-functional storage cells
TL;DR: In this article, a tri-state driver is used to disable the memory array chip associated with a particular chip driver when a defective memory cell location thereof is addressed, and to enable the substitution memory chip at the particular location and connect it to the data bus in place of the associated memory array chips.
Patent
Fault-tolerant memory system
TL;DR: A logical addressing scheme as discussed by the authors treats the memory as having P pages, each with N multibit memory words, and each module provides one bit of memory at the same bit position in every word in the page.
Patent
Apparatus for high speed fault mapping of large memories.
TL;DR: In this article, an approach for mapping and classifying the faulty bits of a large computer memory is described, where the faulty memory bits are scattered among accessed data words in such a way that available error correcting capability can correct the remaining faulty bits in each data word.