Patent
Method and apparatus for testing integrated circuit memories
TLDR
In this article, a random sequencer is used to generate a pseudo-random data bit pattern to be written into the cells of a DRAM chip, which can be used to test the functionality and maximum operating speed of the DRAM.Abstract:
A method and apparatus for testing the functionality and maximum operating speed of a dynamic random access memory (DRAM) chip includes a random sequencer circuit for generating a pseudo-random data bit pattern to be written into the cells of a DRAM chip. The apparatus includes a variable clock circuit which produces a continuously variable frequency clock signal to continuously increase the speed at which data is written into the DRAM. During read cycles of the DRAM, data read from the DRAM is compared with the pattern produced by the random sequencer in a comparator, and any non-correspondence between bits will activate an LED to indicate a failure of the chip. In this way, the maximum speed of the chip may be determined to isolate both defective and marginally damaged chips. The apparatus is operated as a stand-alone unit which does not require the use of any software or interfaced host microprocessor.read more
Citations
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Patent
Memory system topologies including a buffer device and an integrated circuit memory device
TL;DR: In this paper, an integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices using a single fly-by (or bus) signal path.
Patent
Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
TL;DR: In this paper, a memory module includes a plurality of signal paths that provide data to the memory module connector interface from an associated plurality of integrated circuit memory devices, and each integrated circuit buffer device is coupled to a bus that provides control information that specifies an access to at least one memory device.
Patent
System including a buffered memory module
TL;DR: In this paper, a master device and a first memory module having a plurality of integrated circuit memory devices and a pluralityof integrated circuit buffer devices that operate in first and second modes of operation (bypass mode) are presented.
Patent
Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
Richard M. Barth,Ely K. Tsern,Craig E. Hampel,Frederick A. Ware,Todd Bystrom,Bradley A. May,Paul G. Davis +6 more
TL;DR: In this paper, a method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus.
Patent
Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories
TL;DR: In this paper, a linear feedback shift register (LFSR) was used for address generation during memory self-testing to increase fault coverage. But the LFSR was not used for data generation.
References
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Patent
Semiconductor memory test equipment
TL;DR: In this paper, a semiconductor memory test equipment which reads out a memory under test by an address from a pattern generator and compares the read-out data with an expected value by a comparator is presented.
Patent
Tester for LSI devices and memory devices
TL;DR: In this paper, a single tester tests both LSI and memory devices by storing test signals and standards for the pins of LSI devices in a storage element, and selectably routing the test signals from the storage element for LSI testing and from the generator for memory testing.
Patent
Dynamic random access memory device provided with test circuit for internal refresh circuit
TL;DR: In this article, the content of an internal address counter is supplied to both the row of column address decoders, by which one memory cell disposed on the diagonal in a memory cell array is designated.
Patent
Memory system having self-adjusting strobe timing
TL;DR: In this article, an adaptive memory system comprising a core memory, utilizing externally generated read strobe pulses, an exerciser which writes a test pattern into the memory, and compares the result with a predetermined desired performance of the memory.
Patent
Method of and system for fast functional testing of random access memories
TL;DR: In this paper, random bits are written successively into the cells of a random access memory (RAM) system, then complemented, through a first sequence of cell addresses distributed substantially uniformly throughout all cells of the memory.