Patent
Method and apparatus for using smart memories in computing
TLDR
In this paper, a smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is described, where the data stored in the smart memory can be accessed just like the conventional main memory, but the execution units also have many execution units to process data in situ.Abstract:
A smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is disclosed. The data stored in the smart memory can be accessed just like the conventional main memory, but the smart memory also has many execution units to process data in situ. The smart memory computing system offers improved performance and reduced costs for those programs having massive data-level parallelism. This smart memory computing system is able to take advantage of data-level parallelism to improve execution speed by, for example, use of inventive aspects such as algorithm mapping, compiler techniques, architecture features, and specialized instruction sets.read more
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Patent
Algorithm mapping, specialized instructions and architecture features for smart memory computing
TL;DR: In this paper, a smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is described, where the data stored in the smart memory can be accessed just like the conventional main memory, but the execution units also have many execution units to process data in situ.
Patent
Apparatuses and methods for performing logical operations using sensing circuitry
TL;DR: In this paper, the authors present an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array, which can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, and perform a number of intermediate operation phases of the logical operation.
Patent
Apparatus and Method for Controlling a Master/Slave System via Master Device Synchronization
TL;DR: In this article, a master/slave system includes the step of identifying a master receive data phase value to coordinate the transfer of data from a slave device without phase alignment circuitry to a master device with a universal phase aligner.
Patent
Apparatuses and methods for performing compare operations using sensing circuitry
TL;DR: In this paper, the authors present apparatuses and methods related to performing compare and/or report operations using sensing circuitry, such as charging an input/output (IO) line of a memory array to a voltage.
Patent
Division operations for memory
TL;DR: In this article, the present disclosure provides apparatuses and methods for performing division operations in a memory, including a first address space comprising a first number of memory cells coupled to a sense line and to a second number of select lines wherein the second address space stores a divisor value.
References
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Patent
Apparatus and method for a memory unit with a processor integrated therein
TL;DR: In this article, a smart memory (10) is provided that includes data storage (12 and 18) and a processing core (14 and 16) for executing instructions stored in the data storage area.
Patent
Smart memory interface
TL;DR: In this paper, a method and apparatus for initiating a start-up operation of a system having a master device (1) and a slave device (14 a -14 n ) is described.
Patent
Computer, memory, telephone, communications, and transportation system and methods
Venson M. Shaw,Steven M. Shaw +1 more
TL;DR: In this paper, a time sharable run-time resource utilization controller and a method of processing information including a scheduling device for receiving and accumulating a number of utilization request signals for assigning a time slot for the beginning and the end of each utilization.
Patent
Information processing system having smart memories
TL;DR: In this paper, an information processing system including a host CPU and a plurality of external memories is disclosed in which each external memory is formed of a smart memory having a large memory capacity, a linear address arrangement and an arithmetic and logical function.