Patent
Method and circuit for substrate current induced hot e-injection (SCIHE) approach for VT convergence at low Vcc voltage
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TLDR
In this article, a method for soft programming memory cells and floating gate memory devices is described. But the method requires a constant current source to the drain, and the well voltage must be at least 4 V lower than the gate voltage.Abstract:
A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.read more
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Patent
Reducing floating gate to floating gate coupling effect
Yupin Fong,Daniel C. Guterman +1 more
TL;DR: In this article, the authors proposed to compress the erase threshold voltage distribution into the lowest threshold voltage state to decrease the valid data threshold voltage window, which reduces the floating gate to floating gate coupling effect.
Patent
Voltage negotiation in a single host multiple cards system
TL;DR: In this paper, a low-cost data storage and communication system has a host and at least one card connected to the host, and a voltage negotiator is located in the system for determining a common operating voltage range that is a common demonminator of all independent operating voltage ranges of all of the cards.
Patent
Semiconductor memory device.
TL;DR: In this paper, the read circuit senses a change in a voltage of the bitline of a bitline, and applies a voltage which is different from the first voltage to the gate of the first transistor when it senses a voltage change.
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Method of programming non-volatile semiconductor memory device
TL;DR: In this paper, a method of programming a nonvolatile semiconductor memory device is provided, which includes a bitline setup step, a well bias setup step and a program step, and a discharge step.
Patent
Flash memory cell for high efficiency programming
TL;DR: A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate as discussed by the authors, and it is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate.
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Patent
Flash EEPROM array with floating substrate erase operation
Jian Chen,Nader Radjy +1 more
TL;DR: In this paper, a flash EEPROM cell array is erased by applying a relatively high positive voltage to the source region and a ground potential to the control gate of the cell while allowing the voltage of the drain region and the substrate region to float.
Patent
Structure and method for low current programming of flash EEPROMs
TL;DR: In this paper, a system and method for programming nonvolatile memory enables fast low-current programming, which is achieved by applying a source bias voltage and increasing the drain voltage to be greater than the source voltage to maintain fast programming.
Patent
Fast flash EPROM programming and pre-programming circuit design
TL;DR: In this paper, a control circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMs is presented. But, it is not shown how to use a voltage source to vary the gate programming potential during a programming interval as a function of time.
Patent
Floating gate or flash EPROM transistor array having contactless source and drain diffusions
TL;DR: In this article, the authors proposed a drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors, and the shared source region is coupled through a bottom block select transistor to a virtual ground terminal.
Patent
Flash eprom with block erase flags for over-erase protection
TL;DR: In this article, a flash memory array is organized into a plurality of blocks of memory cells, and an erase verify circuit is used to separate erasure of blocks in the plurality of block memory cells.