Journal ArticleDOI
Modeling programmable logic controllers for logic verification
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TLDR
A modeling technique has been developed to verify relay ladder logic (RLL), a PLC programming language and the performance of the model checker is studied in a series of alarm designs.Abstract:
Verification method has been developed for determining the safety and operability of programmable logic controller (PLC) based systems. The method automatically checks sequential logic embedded in PLCs and provides counterexamples if it finds errors. The method consists of a system model, assertions, and a model checker. The model is a Boolean-based representation of a PLC's behavior. Assertions are questions about the behavior of the system, expressed in temporal logic. The model checker generates a state space based on the above two inputs, searches the space efficiently, determines the consistency of the model and assertions, and supplies counterexamples. A modeling technique has been developed to verify relay ladder logic (RLL), a PLC programming language. The performance of the model checker is studied in a series of alarm designs. >read more
Citations
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Proceedings ArticleDOI
Formal methods in PLC programming
Georg Frey,Lothar Litz +1 more
TL;DR: A detailed generic model of the control design process is introduced and discussed, used for surveying different formal approaches in the context of PLC programming.
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Design and implementation of PLC-based monitoring control system for induction motor
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Proceedings ArticleDOI
Arcade.PLC: a verification platform for programmable logic controllers
TL;DR: Arcade.PLC is introduced, a verification platform for programmable logic controllers (PLCs) that supports static analysis as well as ACTL and past-time LTL model checking using counterexample-guided abstraction refinement for different programming languages used in industry.
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An overview of model checking practices on verification of PLC software
TL;DR: A broad view is provided about the difficulties that are encountered during the model checking process applied at the verification phase of PLC software production and can be used to provide guidance for the scholars and practitioners planning to integrate model checking to PLC-based software verification activities.
Proceedings ArticleDOI
Efficient representation for formal verification of PLC programs
TL;DR: This paper addresses scalability of model-checking using the NuSMV model-checker and an efficient representation of PLC programs is proposed, which includes only the states that are meaningful for properties proof.
References
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Automatic verification of finite-state concurrent systems using temporal logic specifications
TL;DR: It is argued that this technique can provide a practical alternative to manual proof construction or use of a mechanical theorem prover for verifying many finite-state concurrent systems.
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TL;DR: An overview of discrete-event dynamic system (DEDS) is given, explaining what they are and discussing their modeling, and factors to be taken into account in modeling are examined.
Journal ArticleDOI
Automatic verification of sequential control systems using temporal logic
TL;DR: A model-based verification method is developed and applied to validation of VLSI circuits and to reveal discrete event errors, the method is applied to a simple combustion system and an alarm acknowledge system.
Journal ArticleDOI
Design recovery for relay ladder logic
A. Falcione,Bruce H. Krogh +1 more
TL;DR: An algorithm for converting relay ladder logic programs for programmable logic controllers (PLCs) into sequential function chart (SFC) programs is introduced and several fundamental issues in discrete control logic representation and analysis are identified as fertile areas for future research.