Patent
MOS device structure and method for reducing PN junction leakage
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TLDR
To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly-doped bulk materials, a high concentration region is implanted at the junction as mentioned in this paper, which contains a relatively high dopant level.Abstract:
To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly doped bulk materials, a high concentration region is implanted at the junction. The high concentration region contains a relatively high dopant level, and thus reduces the width of the depletion region at the junction. The reduced width of the depletion region in turn reduces junction leakage.read more
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Method for engineering the threshold voltage of a device using buried wells
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References
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Patent
An integrated semiconductor device having a buried semiconductor layer and fabrication method thereof
Noriaki Sato,Fumitake Mieno +1 more
TL;DR: In this article, a well is formed in the semiconductor substrate within windows of a field oxide layer, and a lightly-doped semiconductor layer is selectively formed on the exposed surface of the well.