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Patent

Multiple branch predictions

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TLDR
In this paper, branch prediction for multiple branch-type instructions is performed concurrently for a high-bandwidth pipeline, and the branch prediction is then supplied for further processing of the corresponding branch type instructions.
Abstract
Concurrently branch predicting for multiple branch-type instructions satisfies demands of high performance environments. Concurrently branch predicting for multiple branch-type instructions provides the instruction flow for a high bandwidth pipeline utilized in advanced performance environments. Branch predictions are concurrently generated for multiple branch-type instructions. The concurrently generated branch predictions are then supplied for further processing of the corresponding branch-type instructions.

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Citations
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Resit Sendag
TL;DR: In this article, a system for branch misprediction prediction in a microprocessor is described, which includes a mispredicted branch table that includes address, distance, and true/not true fields.
References
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Patent

Performance monitoring of thread switch events in a multithreaded processor

TL;DR: In this paper, a multithreaded processor and a method for performance monitoring within a multi-threaded processor are described, where thread switch logic switches threads by activating the inactive thread and inactivating the active thread.
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Simultaneous prediction of multiple branches for superscalar processing

TL;DR: In this article, the authors present a system and method for predicting a multiplicity of future branches simultaneously from an executing program, to enable the simultaneous fetching of multiple disjoint program segments.
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A cache system for concurrent processes

TL;DR: In this article, a cache memory is divided into cache partitions, each cache partition having a plurality of addressable storage locations for holding items in the cache memory, and a partition indicator is allocated to each process identifying which of the cache partitions is to be used for hold items for use in the execution of that process.
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Superscalar microprocessor stack structure for judging validity of predicted subroutine return addresses

TL;DR: In this article, a return stack is described which stores return addresses associated with subroutine call instructions along with an ESP register value associated with the sub-routine calls in a stack-type structure.