Patent
Nanostructures, assembling method for nanowires, and device assembled from nanowires
Rong Fan,Henning Feick,Michael H. Huang,Hannes Kind,Arun Majumdar,Samuel S. Mao,Richard E. Russo,Timothy D. Sands,Ali Shakouri,Eicke R. Weber,Yiying Wu,Haoquan Yan,Peidong Yang,ウー,イーイン,アール ウェバー,エイケ,キント,ハンネス,ディー サンズ,ティモシー,シャコウリ,アリ,ファン,ロン,フェイック,ヘニング,ホアン,マイケル,エス マオ,サミュエル,マジュンダー,アラン,ヤン,ハオチュアン,ヤン,ペイドン,イー ルッソ,リチャード +25 more
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TLDR
In this paper, the authors proposed to provide one-dimensional nanostructures having diameters along a vertical axis wherein the diameters do not change nearly 10% or more at a section showing the maximum diameter change and the maximum diameters of less than approximately 200 nm, regarding substantially crystalline nanowire structures.Abstract:
PROBLEM TO BE SOLVED: To provide one-dimensional nanostructures having diameters along a vertical axis wherein the diameters do not change nearly 10% or more at a section showing the maximum diameter change and the maximum diameters of less than approximately 200 nm, regarding substantially crystalline nanowire structures. SOLUTION: The one-dimensional nanostructures have the uniform diameters of less than approximately 200 nm. The new nanostructures called as "nanowires" include single-crystalline homostructures as well as heterostructures of two single-crystalline materials having different chemical compositions. The resulting heterostructures similarly become single crystals since the single-crystalline materials are used for forming the heterostructures. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire including different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN). COPYRIGHT: (C)2011,JPO&INPITread more
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Method for manufacturing nanowire
TL;DR: In this article, a nanowire of a group III-V compound on graphene was formed by an organometallic vapor phase growing method using the metallic particulates as a catalyst.
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Quantum fine line device and manufacture
TL;DR: In this article, an Au thin film is formed on a silicon single crystalline substrate by sputtering method, resist is applied thereto, a pattern is formed by photolithography method, dry etching is performed for EB and an AU thin film layer is etched.
Patent
Element having thin wire and its manufacture
Pal Gosain Durham,Westwater Jonathan,Miyako Nakakoshi,Setsuo Usui,ウエストウォータ ジョナサン,パル ゴサイン ダラム,美弥子 中越,節夫 碓井 +7 more
TL;DR: In this article, the formation support film on the substrate is formed by forming holes corresponding to the formation positions of the respective thin wires, forming one fused alloy drop in each hole by vapor-depositing and heating gold and supplying SiH4 and growing the corresponding thin wires below the respective fused alloy drops respectively.
Patent
Quantum fine line structure and its manufacture
TL;DR: In this article, a quantum fine line structure is a needle semiconductor crystal which is formed epitaxially on a semiconductor substrate crystal 8, has a hetero junction structure which consists of the crystal 3 whose central part is formed of the needle crystal and of crystals 4, 5 which form a peripheral part enclosing it concentrically.
Patent
Production of quantum fine line
Pal Gosain Daram,Westwater Johnathan,Miyako Nakakoshi,Setsuo Usui,ウエストウォータ ジョナサン,パル ゴサイン ダラム,美弥子 中越,節夫 碓井 +7 more
TL;DR: In this paper, the problem of growing a silicon quantum fine line having a sufficiently small diameter is addressed. But the size of the line has not yet been determined, and it is not known how to obtain a small diameter.
Patent
Manufacture of quantum thin line
Daramu Paru Gosain,Jonathan Westwater,Miyako Nakakoshi,Setsuo Usui,ウエストウォータ ジョナサン,パル ゴサイン ダラム,美弥子 中越,節夫 碓井 +7 more
TL;DR: In this paper, the authors proposed a manufacturing method for growing a silicon quantum thin line with a good shape, where gold is subjected to vapor deposition on a silicon substrate (Si) 11 and the thickness of gold is 5nm or below.