Patent
Non-volatile memory
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TLDR
In this article, the reference voltage is between QI/CD and QSW/CD + QI+CD, where QI is the linear capacitance of the first ferroelectric capacitor, CD is the capacitance for the bit line, and switching charge is the switching charge.Abstract:
A ferroelectric, non-volatile memory (336) includes a constant voltage source (85), a bit line (79), a memory cell (70) having a first ferroelectric capacitor (76) connected between the bit line (79) and the constant voltage source (85), a source (105) of a reference voltage, and a latch (74) connected between the bit line (79) and the reference voltage source (105). The latch (74) drives the bit line (79) to the same logic state as the ferroelectric capacitor (76) to read and rewrite the capacitor (76) in a single operation. The reference voltage is between QI/CD and QSW/CD + QI/CD, where QI is the linear capacitance of said first ferroelectric capacitor (76), CD is the capacitance of said bit line (79), and QSW is the switching charge of said first ferroelectric capacitor (76). In one embodiment, the reference voltage is provided by a ferroelectric dummy capacitor (141) having an area smaller than the area of the first capacitor (128) but greater than 1/2 the area of the first capacitor (128).read more
Citations
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References
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Patent
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TL;DR: In this article, a semiconductor memory with a ferroelec-tric capacitor having one plate coupled to a bit line by a FET and another plate coupled on a plate line is described.
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Klaus Dimmler,S. Sheffield Eaton +1 more
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