Patent
Non-volatile semiconductor memory
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TLDR
In this article, a tunneling mechanism is used to lower the drain voltage at the time of programming of data, so that degradation of a gate oxide film at a channel portion can be mitigated.Abstract:
Each memory cell of a non-volatile semiconductor memory essentially consisting of a one-transistor type memory cell comprising only of an MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Particularly because the negative voltage is used for the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.read more
Citations
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References
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Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems
TL;DR: In this article, the authors describe an electronic system for a memory system and its controller within a single memory card, where the cards utilize a main circuit board with a plurality of sub-boards attached on both sides, each sub-board carrying several integrated circuit chips.
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Nonvolatile semiconductor memory device having row decoder supplying a negative potential to word lines during erasing mode
Atsumi Sigeru,Danaka Sumio +1 more
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Non-volatile semiconductor memory device incorporating data latch and address counter for page mode programming
TL;DR: In this article, a column latch and a high voltage switch connected to each bit line are eliminated, and an address counter and the data latch are newly provided, arranged between an I/O buffer and a Y gate.
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Single transistor eeprom memory cell
TL;DR: In this article, a single-transistor nonvolatile memory cell MOS transistor with a floating gate and a control gate using two levels of polysilicon and a tunnel dielectric that overlaps the drain area was presented.
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Semiconductor integrated circuit
TL;DR: In this paper, the authors propose a system of the absolute necessary number of chips by enabling one chip to be viewed selectively in plural address spaces as to the semiconductor integrated circuit which can optionally select the correspondence relation between a chip select signal and the address spaces.