Proceedings ArticleDOI
Optimal allocation of computational resources in VLSI
Kedem
- pp 379-385
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This article is published in Foundations of Computer Science.The article was published on 1982-01-01. It has received 6 citations till now. The article focuses on the topics: Resource management & Memory management.read more
Citations
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Proceedings ArticleDOI
On notions of information transfer in VLSI circuits
TL;DR: It is shown the fooling set approach is not the most powerful way to get information-transfer-based lower bounds, and a candidate for the title “most powerful” is offered.
Journal ArticleDOI
Area-time lower-bound techniques with applications to sorting
TL;DR: Regimes corresponding to each of the three mechanisms described above can appear by varying the problem parameters, as this work shall illustrate by analyzing the problem of sortingn keys each ofk bits, for whichAT2,AT, andAT/logA bounds are derived.
Book ChapterDOI
On Restricted Boolean Circuits
TL;DR: Bounds are given comparing the computational power of circuits from these classes of restricted Boolean circuits: synchronous and locally synchronous circuits, planar circuits, formulas and multilectivePlanar circuits.
Journal ArticleDOI
On the complexity of planar Boolean circuits
TL;DR: It is shown that planar circuits and formulas are incomparable and an Ω(n3/2) lower bound is given for the multilective planar circuit complexity of a multiple output function.
Journal ArticleDOI
Multiple cuts, input repetition, and VLSI complexity
TL;DR: Revue des methodes de coupures multiples appliquees a la determination de la complexite des circuits VLSI, basees sur une definition generalisee du «contenu d'information», s'agissent aux problemes autorisant ou non la repetition des entrees.
References
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Proceedings ArticleDOI
Area-time complexity for VLSI
TL;DR: The complexity of the Discrete Fourier Transform is studied with respect to a new model of computation appropriate to VLSI technology, which focuses on two key parameters, the amount of silicon area and time required to implement a DFT on a single chip.
Journal ArticleDOI
The Area-Time Complexity of Binary Multiplication
TL;DR: By using a model of computation which is a realistic approx~mauon to current and anucipated LSI or VLSI technology, it is shown that A T 2.0 is shown to be the time required to perform multtphcaUon of n-bit binary numbers on a chip.
Proceedings ArticleDOI
The entropic limitations on VLSI computations(Extended Abstract)
TL;DR: The limitations imposed by entropic constraints, both in generality and for specific problems, are explored, including in the binary number system, while addition is easy while multiplication is hard for VLSI.
Proceedings ArticleDOI
A combinatorial limit to the computing power of V.L.S.I. circuits
TL;DR: In this paper, it was shown that the area of any circuit computing a transitive function grows quadratically with the circuit's maximum data-rate, expressed in bit/second.
Proceedings ArticleDOI
A model of computation for VLSI with related complexity results
Bernard Chazelle,Louis Monier +1 more
TL;DR: A new model of computation for VLSI is proposed which is a refinement of previous models and makes the additional assumption that the time for propagating information is linear in the distance, which makes it especially suited for deriving lower bounds and trade-offs.
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