Overview of the CHiP Computer

TLDR: It is argued on the basis asymptotic analysis that a constant corridor width is preferred even though such lattices cannot make full use of the processor elements for most complex interconnection patterns, e.g., universal interconnection structures like the cube connected cycles and shuffle exchange.

Abstract: : The main question under study is how wide the corridor width should be for the switch lattice of the Configurable, Highly Parallel (CHiP) computer. (The CHiP computer family is introduced and its use for parallel algorithm composition is motivated.) It is argued on the basis asymptotic analysis that a constant corridor width is preferred even though such lattices cannot make full use of the processor elements for most complex interconnection patterns, e.g., universal interconnection structures like the cube connected cycles and shuffle exchange, and for certain 'simple' ones, e.g., certain planar graphs. (Author)