Patent
Pipeline signal processor
TLDR
In this article, a signal processor including a programmable arithmetic controller and a pipeline arithmetic unit controlled by such controller is described, where the arithmetic unit includes a plurality of serially coupled processing levels.Abstract:
A signal processor including a programmable arithmetic controller and a pipeline arithmetic unit controlled by such controller is disclosed. The arithmetic unit includes a plurality of serially coupled processing levels. The arithmetic controller includes a corresponding plurality of serially coupled control levels, each one of such control levels being coupled to a corresponding one of the processing levels. Each one of the processing levels passes digital data applied thereto in accordance with a control instruction applied to such processing level by the arithmetic controller. As data passes through the various processing levels, the control instruction associated with such data passes through the corresponding control level so that such control instruction ''''follows'''' such data as both data and control instruction pass through the processor. In this way the processor is adapted to start a new process concurrently as such processor completes a prior process.read more
Citations
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Patent
Multistandard video decoder and decompression system for processing encoded bit streams including a video formatter and methods relating thereto
Adrian Philip Wise,Martin William Sotheran,William Philip Robbins,Anthony Mark Jones,Helen Rosemary Finch,Kevin James Boyd,Anthony Peter John Claydon +6 more
TL;DR: In this article, a pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bits stream.
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TL;DR: In this paper, the vector processing in a computer is achieved by means of a plurality of vector registers, independent fully segmented functional units, and means for controlling the operation of the vector registers.
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TL;DR: In this article, a pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bits stream.
Patent
Multinode reconfigurable pipeline computer
TL;DR: In this article, a multinode parallel-processing computer is made up of a plurality of inner-connected, large capacity nodes each including a reconfigurable pipeline of functional units such as Integer Arithmetic Logic Processors, Floating Point Arithmetic Processors and Special Purpose Processors.
Patent
Digital signal processor
Tokumichi C,O Mitsubishi Denki K.K. Murakami,Koh C,O Mitsubishi Denki K.K. Kamizawa,Naoto C,O Mitsubishi Denki K.K. Kinjo,Hideo C,O Mitsubishi Denki K.K. Ohira,Takao C,O Mitsubishi Denki K.K. Wakabayashi +9 more
TL;DR: In this article, a digital signal processor is used for motion compensation in order to reduce a required amount of calculations when an amount of distortion between a last frame block and a current frame block is minimized.
References
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Patent
Apparatus and method for serializing instructions from two independent instruction streams
Joseph Orazio Celtruda,William Russell Crosthwait,John Goodell Earle,Jun John Wenard Fennel,Roy Francis Henderson +4 more
TL;DR: In this article, an apparatus for sharing the processing capability of a digital computer between two independent instruction streams is described, which includes a buffer for instructions of each of the independent instructions, connected to a selection means which samples various machine resources and determines which instruction of the two independent instructions is to be executed next.
Patent
Pipelined high speed arithmetic unit
Stephenson C,Watson W +1 more
TL;DR: In this paper, a digital computer central processing unit is disclosed having an arithmetic unit which forms an element of an instruction processing pipeline, and the arithmetic unit has within it a plurality of arithmetic subunits each with its own storage and partitioned on a functional basis for the simultaneous execution of a pluralityof arithmetic steps within the arithmetic units while a plurality-of- instructions are simultaneously processed in their flow to the assembly.
Patent
Data processor with parallel operations per instruction
TL;DR: In this paper, an instruction format includes multiple fields which separately identify operations to be executed in parallel at each clock-time in response to a single instruction drawn from an instruction memory, which is achieved as a consequence of implementing the internal data registers and arithmetic circuits with multiple data inputs.