Patent
Power, ground and decoupling structure for chip carriers
TLDR
In this paper, the chip is hermetically sealed within the ceramic cap which is bonded to the chip carrier and a dielectric sliver which rests above a glass filler and bonding agent which fills the space between the interdigitated pattern and the sliver.Abstract:
A chip carrier having a plurality of leads thereon for external interconnection with preferably only one of the leads utilized to provide a source of power to the chip and preferably a single lead utilized as a ground connection. The power and ground leads are connected to an interdigitated lead array at the center of the chip carrier with the chip being secured to the chip carrier above the interdigitated pattern. The chip is bonded to a dielectric sliver which rests above a glass filler and bonding agent which fills the space between the interdigitated pattern and the sliver. The chip is hermetically sealed within the ceramic cap which is bonded to the chip carrier. Power and ground connections are made, from the chip directly to a pair of buses surrounding the interdigitated pattern rather than to leads extending outwardly to the edge of the chip carrier.read more
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Patent
Semiconductor chip assemblies with fan-in leads
TL;DR: In this article, a semiconductor chip having contacts on the periphery of its top surface is provided with an interposer overlying the central portion of the top surface, where peripheral contact leads extend inwardly from the peripheral contacts to central terminals on the interposers.
Patent
Semiconductor chip assemblies, methods of making same and components for same
TL;DR: In this paper, a flexible, sheet-like element having terminals thereon overlying the front or rear face of the chip is used to provide a compact unit. But, the terminals on the sheetlike element are movable with respect to the chip, so as to compensate for thermal expansion.
Patent
Fabricating interconnects and tips using sacrificial substrates
TL;DR: In this paper, the authors describe the fabrication of interconnection elements (752) and tip structures (770) formed as cantilever beams for electronic component mounting, where the tip structures are joined to the free-ends of the interconnection element.
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Methods of making semiconductor chip assemblies
TL;DR: In this article, a method of making semiconductor chip assemblies includes providing a semiconductor wafer including a plurality of semiconductor chips having contacts on a contact bearing surface thereof, and providing a substrate having a first surface with conductive terminals located thereon and a second surface.
Patent
Thin film capacitor coupons for memory modules and multi-chip modules
James M. Wark,Salman Akram +1 more
TL;DR: In this article, a capacitor coupon is mounted on the backside of a semiconductor die and the coupon is secured by flip-chip connections or direct chip attach between the die and substrate.
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Patent
Conductively coated embossed articles
TL;DR: In this paper, embossed patterns in bas-relief are used to provide conductors for high speed automatic processing and further have improved electrical properties particularly for high frequency applications, especially for high-frequency applications.
Patent
Metal-insulator-metal solid-state rectifier
TL;DR: In this article, a metal-insulator-metal layered structure is disclosed which is useful as a rectifier of AC voltage, one of the metal layers is advantageously in the form of a crossgrid-type geometry, in order to afford a large perimeter of contact with the insulator layer.