Patent
Pulsed circuit topology including a pulsed, domino flip-flop
Reads0
Chats0
TLDR
In this article, a pulsed circuit topology with a flip-flop and a latch responsive to a first pulsed clock input signal is provided to latch data indicated at the domino output node.Abstract:
A pulsed circuit topology including a pulsed domino flip-flop. A circuit includes a domino logic gate having a domino output node responsive to input data during an evaluate pulse. Reset circuitry initiates and self-terminates a reset pulse during which the domino output node is precharged. A latch responsive to a first pulsed clock input signal is provided to latch data indicated at the domino output node.read more
Citations
More filters
Patent
Exogenous proteins expressed in avians and their eggs
TL;DR: In this paper, a method for the stable introduction of exogenous nucleic acid sequences into the genome of avians in order to express the exogenous sequences to alter the phenotype of the avians or to produce desired proteins was proposed.
Patent
N-domino register with accelerated non-discharge path
Imran Qureshi,Raymond A. Bertram +1 more
TL;DR: A P-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path and an output stage as mentioned in this paper.
Patent
Unified instruction pipeline for power reduction in a digital signal processor integrated circuit
Ruban Kanapathippillai,Kumar Ganapathy,Thu Nguyen,Siva Venkatraman,Earle F. Philhower,Manoj Mehta,Kenneth Malich +6 more
TL;DR: In this article, the authors propose a method for reducing power consumption in a digital specific signal processor integrated circuit (DSP) by using a loop buffer to store instructions within program loops to avoid memory accesses.
Patent
Self-timed activation logic for memory
TL;DR: In this paper, a self-timed logic circuit is used to generate a self timed memory clock to access data in a memory, which has a periodic pulse which enables circuitry in the memory for a brief period of time over its pulse width.
Patent
Limited switch dynamic logic circuit with keeper
TL;DR: In this paper, the output and the dynamic node are both at a logic one when the output is a logic zero from the previous evaluation cycle, and a keeper PFET is added by coupling its drain terminal to the dynamic nodes.
References
More filters
Patent
Self-enabling pulse trapping circuit
TL;DR: In this article, an integrated circuit memory device is described which can operate at high data speeds and can either store or retrieve data from the memory in a burst access operation, where burst operations latches a memory address from external address lines and internally generates additional memory addresses.
Patent
Clocking scheme for latching of a domino output
TL;DR: In this article, a clocking scheme is proposed to delay a precharging of a domino node by introducing a delay in the clocking circuitry, which activates the precharging.
Patent
Opportunistic time-borrowing domino logic
TL;DR: In this paper, an opportunistic time-borrowing domino logic includes a domino pipeline having a plurality of logic gates coupled in series and controlled by first, second, third and fourth clock signals.
Patent
Multiple frequency output clock generator system
TL;DR: In this article, a clock generator system for multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison.
Patent
Pulsed domino latches
TL;DR: In this article, a static logic block is connected to one input of a domino evaluation tree, which operates only during a brief window of time, while an evaluation control block is ON.