Patent
Semiconductor memory device including clock generation circuit
TLDR
In this article, a DLL circuit generates first and second internal clocks delayed by appropriate quantities from an external clock, and generates third and fourth internal clocks capable of driving a data output circuit after a CAS latency.Abstract:
A DLL circuit generates first and second internal clocks delayed by appropriate quantities from an external clock, and generates third and fourth internal clocks capable of driving a data output circuit after a CAS latency from the first and second internal clocks on the basis of an internal signal. A repeater recovers signal levels of the third and fourth internal clocks and outputs the third and fourth internal clocks as DLL clocks. The data output circuit takes in read data using the DLL clocks outputted from the repeater, and outputs the read data to an outside in a half cycle synchronously with the DLL clocks. In this way, a circuit area of a semiconductor memory device can be reduced by generating the DLL clocks in a prior stage to the data output circuit.read more
Citations
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Patent
Internal voltage generation circuit of semiconductor device
TL;DR: An internal voltage generation circuit of a semiconductor device includes: a comparator for comparing a reference voltage level with a detection voltage level to provide a comparison signal, an internal voltage output device for raising a voltage of an external voltage output terminal to a predetermined level in response to the comparison signal.
Patent
Data output control circuit
TL;DR: A data output control circuit for use in a synchronous semiconductor memory device including a first data output enable signal generation unit for receiving an internal signal and generating a rising data output enabled signal synchronizing with a rising edge of a DLL clock signal according to a CAS latency was proposed in this article.
Patent
Delayed locked loop circuit
TL;DR: A delay locking loop circuit for compensating for a phase skew of a memory device includes a first delay locking unit configured to delay an external clock of the memory device by a first amount of delay to output a first internal clock as discussed by the authors.
Patent
Delay locked loop circuit of semiconductor device
Hee-Woong Song,Kunwoo Park,Yong-Ju Kim,Ic-Su Oh,Hyungsoo Kim,Tae-jin Hwang,Hae-Rang Choi,Ji Wang Lee +7 more
TL;DR: In this article, a phase comparator is used to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference.
Patent
Semiconductor memory device, semiconductor system including the semiconductor memory device, and method for operating the semiconductor memory device
TL;DR: In this paper, the authors describe a memory device that includes a first data input/output unit configured to receive a normal training data, whose data window is scanned based on an edge of a source clock, in response to a training input command, and output a data in a state where an edge is synchronized with the edge of the source clock in response of a training output command.
References
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Patent
Semiconductor storage device with suppressed power consumption and reduced recovery time from suspend mode
TL;DR: In this article, an internal clock signal generating circuit includes a phase comparing circuit which is made active in accordance with a control signal SEN which becomes intermittently active in a power down mode from an operation permission signal generator circuit.
Patent
Delay locked loop circuit
Yoshinori Haraguchi,嘉典 原口 +1 more
TL;DR: In this paper, the authors proposed to prevent a wrong lock state caused by the manufacturing variance of a DLL(delay-locked loop) circuit by doubling the sampling cycle of phase detection against the cycle of DLL output clock.