Patent
Semiconductor processing methods of forming stacked capacitors
TLDR
In this article, an insulating layer is provided above the nitride oxidation barrier layer, and an contact/container is etched there through and through dielectric and cell polysilicon layers.Abstract:
In one aspect of the invention, an insulative nitride oxidation barrier layer is provided over a cell polysilicon layer to a thickness of at least about 150 Angstroms. An insulating layer is provided above the nitride oxidation barrier layer, and an contact/container is etched therethrough and through dielectric and cell polysilicon layers. Such exposes edges of the cell polysilicon within the contact/container. The wafer is then exposed to an oxidizing ambient to oxidize the cell polysilicon exposed edges, with the nitride oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell polysilicon layer. In another aspect, a multi-container stacked capacitor construction has its containers defined or otherwise electrically isolated in a single CMP step. In another aspect, a combination etch stop/oxidation barrier layer or region is provided to enable exposure of a precise quantity of the outside walls of a stacked capacitor container.read more
Citations
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References
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Patent
Method of forming a stacked capacitor with striated electrode
Guy T. Blalock,Phillip G. Wald +1 more
TL;DR: In this paper, a method of forming a capacitor on a semiconductor wafer includes: a) in a dry etching reactor, selectively anisotropically dry, etching a capacitor contact opening having a minimum selected open dimension into an insulating dielectric layer utilizing selected gas flow rates of a reactive gas component and an inert gas bombarding component, the flow rate of the bombarded component significantly exceeding the reactive component to effectively produce a capacitance opening having grooved striated sidewalls and thereby defining female capacitance.
Patent
Method for formation of a stacked capacitor
TL;DR: In this paper, a method for forming a capacitance on a semiconductor wafer which utilizes top and back sides of a capacitor node for capacitance maximization is disclosed. But the method is not suitable for the case of high voltage.
Patent
Method of manufacturing DRAM cell having a cup shaped polysilicon storage electrode
TL;DR: In this article, a DRAM cell of a stack structure having a cup-shaped polysilicon storage electrode for being applied to a 16 mega and 64 mega DRAM wherein a transfer transistor is firstly manufactured, a bit line is formed, an oxide film grid is formed between the cell and cell in the minimum design rule, and upon completing this, the storage electrode is formed into a single or double cup shape.
Patent
Method of forming contacts to a semiconductor device
San-Mei Ku,Katleen Alice Perry +1 more
TL;DR: In this paper, a method of forming semiconductor device contacts includes the steps of: providing a semiconductor substrate (26) having at least two features e.g. a polysilicon land (36), another polysilico land (48), and a substrate(26), thereon whereat it is desired to make electrical connections; forming a layer (54) of etch stop material having a first etch characteristic over each of the features; forming an etchant selective to the layer of dielectric material so as to substantially stop on the layer, the at least
Patent
Semiconductor integrated circuit device
TL;DR: In this article, the memory circuit includes a decoder for externally applied time multiplexed address signal supplied to the decoder on address signal lines, the address signals include a row address portion followed by a column address portion.