Journal ArticleDOI
Several Key Issues on Implementing Delay Line Based TDCs Using FPGAs
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In this paper, the Wave Union TDC, a novel scheme of FPGA TDC to improve time measurement precision using multiple measurements, along with several other topics in FPGAs delay line based TDCs.Abstract:
This paper discusses implementation of the Wave Union TDC, a novel scheme of FPGA TDC to improve time measurement precision using multiple measurements, along with several other topics in FPGA delay line based TDCs. FPGA specific issues such as considerations on the delay line choice in different FPGA families and encoding logic are first examined. Next, common problems for both FPGA TDCs and ASIC TDCs such as schemes of coarse time counter implementation, bin-by-bin calibration and noise issues due to single ended signals are discussed. Several resource/power saving design approaches for various processing stages are described in the document.read more
Citations
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Voltage drop-based fault attacks on FPGAs using valid bitstreams
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The 10-ps Multitime Measurements Averaging TDC Implemented in an FPGA
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References
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Journal ArticleDOI
A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays
Jian Song,Qi An,Shubin Liu +2 more
TL;DR: A high-resolution time-to-digital converter implemented in a general purpose field-programmable-gate-array (FPGA) is presented and dedicated carry lines of an FPGA are used as delay cells to perform time interpolation within the system clock period and to realize the fine time measurement.
Proceedings ArticleDOI
The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay
Jinyuan Wu,Zonghan Shi +1 more
TL;DR: The “wave union launchers” described in this paper are designed to make multiple measurements with a single delay chain structure, effectively to sub-divide the ultra-wide bins in each raw measurement.
Proceedings ArticleDOI
Firmware-only implementation of time-to-digital converter (TDC) in field-programmable gate array (FPGA)
Jinyuan Wu,Zonghan Shi,I.Y. Wang +2 more
TL;DR: A Time-to-Digital Converter implemented in general purpose field-programmable gate array, (FPGA) for the Fermilab CKM experiment will be presented and several digital compensation strategies that can be implemented in the same FPGA device will be studied.
Proceedings ArticleDOI
High-precision TDC in an FPGA using a 192 MHz quadrature clock
M.D. Fries,J.J. Williams +1 more
TL;DR: In this paper, a trigger pulse edge detection circuit is used to measure the arrival time of a positron-electron pair within a body that produces a pair of gamma-ray photons.
Journal ArticleDOI
A fully fledged TDC implemented in field-programmable-gate-arrays
TL;DR: In this article, the authors implemented a fully fledged FPGA-based TDC in XILINX XC4VFX60 FPGAs, with the features of Self-Test, temperature variation compensation and trigger-matching.
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