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Proceedings ArticleDOI

Voltage drop-based fault attacks on FPGAs using valid bitstreams

TLDR
This paper reveals a security vulnerability in FPGAs that allows a valid configuration to generate severe voltage fluctuations, which crashes the FPGA within a few microseconds, and analyzes its underlying mechanism.
Abstract
Due to the widespread use of FPGAs in many critical application domains, their security is of high concern. In recent systems, such as FPGAs in the Cloud or in Systems-on-Chip (SoCs), users can gain access, even remotely, to the reconfigurable fabric to implement custom accelerators. This access can expose new security vulnerabilities in the entire system through malicious use of the FPGA fabric. In the past, attacks on the power supply level required local access to the hardware. In this paper, we reveal a security vulnerability in FPGAs that allows a valid configuration to generate severe voltage fluctuations, which crashes the FPGA within a few microseconds. Moreover, the extent of this crash is so severe, that manual power-cycling is required to be able to access and use the system again. This vulnerability has been systematically exploited in two different generations of FPGAs, and a SoC containing an FPGA. Because this vulnerability can lead to severe security attacks in systems using FPGA-based accelerators, we also analyze its underlying mechanism, and discuss possibilities for mitigation.

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Citations
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Proceedings ArticleDOI

FPGA-Based Remote Power Side-Channel Attacks

TL;DR: This work introduces and demonstrates remote power side-channel attacks using an FPGA, showing that the common assumption that powerSideChannel attacks require specialized equipment and physical access to the victim hardware is not true for systems with an integrated FPGAs.
Proceedings ArticleDOI

FPGAhammer: Remote Voltage Fault Attacks on Shared FPGAs, suitable for DFA on AES

TL;DR: This work shows how fault attacks can be launched within an FPGA, through software-provided bitstreams alone, and analyze and adapt an existing fault model for the Advanced Encryption Standard to match the accuracy of the fault attack.
Proceedings ArticleDOI

A Survey on FPGA Virtualization

TL;DR: This survey identifies and classify the various techniques and approaches for FPGA virtualization into three main categories: 1)Resource level, 2)Node level, and 3)Multi-node level.
Proceedings ArticleDOI

Timing Violation Induced Faults in Multi-Tenant FPGAs

TL;DR: This work presents an attack method for causing timing-constraints violation in the multi-tenant FPGA setting, and demonstrates the attack on a set of self-timed true random number generators (STRNGs), frequently used in cryptographic applications.
Proceedings ArticleDOI

RAM-Jam: Remote Temperature and Voltage Fault Attack on FPGAs using Memory Collisions

TL;DR: A novel remote fault attack, called RAM-Jam, is presented, which exploits an existing weakness in the dual port RAMs of mainstream FPGAs, which leads to severe voltage drops and excessive heat that result in timing faults as well as bit-flips in the FPGA's configuration memory.
References
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Journal ArticleDOI

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Proceedings ArticleDOI

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Trustworthy Hardware: Identifying and Classifying Hardware Trojans

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Book ChapterDOI

Breakthrough silicon scanning discovers backdoor in military chip

TL;DR: Using an innovative patented technique, Pipeline Emission Analysis (PEA) was able to extract the secret key to activate the backdoor, as well as other security keys such as the AES and the Passkey, which means the device is wide open to intellectual property (IP) theft, fraud, re-programming, and reverse engineering of the design.
Proceedings ArticleDOI

From opencl to high-performance hardware on FPGAS

TL;DR: It is shown that the OpenCL computing paradigm is a viable design entry method for high-performance computing applications on FPGAs and that it can achieve a clock frequency in excess of 160MHz on benchmarks.
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