Journal ArticleDOI
Shared Cache for Multiple-Stream Computer Systems
TLDR
Cache memory organization for parallel-pipelined multiprocessor systems is evaluated and a shared cache is evaluated, which can attain a higher hit ratio and suffers performance degradation due to access conflicts.Citations
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Proceedings ArticleDOI
A low-overhead coherence solution for multiprocessors with private cache memories
TL;DR: This paper presents a cache coherence solution for multiprocessors organized around a single time-shared bus that aims at reducing bus traffic and hence bus wait time and increases the overall processor utilization.
Parallel Supercomputing Today and the Cedar Approach (並列処理ハ-ドウェアと言語特集)
TL;DR: The Cedar supercomputer as discussed by the authors uses advanced system and applications developed at the University of Illinois during the past 12 years, which should allow the number of processors in Cedar to be doubled annually, providing rapid performance advances in the next decade.
Journal ArticleDOI
Parallel supercomputing today and the cedar approach
TL;DR: The Cedar supercomputer as mentioned in this paper uses advanced system and applications developed at the University of Illinois during the past 12 years, which should allow the number of processors in Cedar to be doubled annually, providing rapid performance advances in the next decade.
Journal ArticleDOI
Essential Issues in Multiprocessor Systems
Gajski,Jib-Kwon Peir +1 more
TL;DR: A suitable classification scheme for comparing these architectures with the aim of determining the predominant importance of new parallel algorithms for enhancement of computer performance is proposed.
Patent
Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
TL;DR: A cache memory capable of concurrently accepting and working on completion of more than one cache access from a plurality of processors connected in parallel is discussed in this paper. But the work in this paper is restricted to the case of a single processor.
References
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Journal ArticleDOI
A study of replacement algorithms for a virtual-storage computer
TL;DR: One of the basic limitations of a digital computer is the size of its available memory; an approach that permits the programmer to use a sufficiently large address range can accomplish this objective, assuming that means are provided for automatic execution of the memory-overlay functions.
Journal ArticleDOI
The working set model for program behavior
TL;DR: A new model, the “working set model,” is developed, defined to be the collection of its most recently used pages, which provides knowledge vital to the dynamic management of paged memories.
Journal ArticleDOI
A New Solution to Coherence Problems in Multicache Systems
TL;DR: A memory hierarchy has coherence problems as soon as one of its levels is split in several independent units which are not equally accessible from faster levels or processors.
Proceedings ArticleDOI
C.mmp: a multi-mini-processor
William A. Wulf,C. G. Bell +1 more
TL;DR: An overview of the goals, design, and status of this hardware/software complex, and some of the research problems raised and analytic problems solved in the course of its construction are described.
Journal ArticleDOI
Structural aspects of the system/360 model 85: II the cache
TL;DR: The cache, a high-speed buffer establishing a storage hierarchy in the Model 85, is discussed in depth in this part, since it represents the basic organizational departure from other SYSTEM/360 computers.