Patent
Signaling protocol for concurrent bus access in a multiprocessor system
TLDR
In this paper, an improved signaling protocol for use in a multiprocessor system enables concurrent access to a common system bus during an I/O bus access, without introducing complexities into the system bus architecture which might otherwise reduce the overall bus bandwidth increase.Abstract:
An improved signaling protocol for use in a multiprocessor system enables concurrent access to a common system bus during an I/O bus access. This reduces the system bus idling time without introducing complexities into the system bus architecture which might otherwise reduce the overall bus bandwidth increase. The improved bus architecture uses a system generated I/O bus busy (IOBUS-- BSY-) signal to indicate to all of the processors that the I/O bus is in use and that all other I/O requests must be held until the current transaction is completed. By preventing the other processors from executing an I/O request, the system bus does not have to be remain idle and can be used for memory-to-processor and for processor-to-processor transactions while the I/O bus is in use. By reducing the amount of time that the system bus is idle, the overall system bus performance is greatly increased.read more
Citations
More filters
Patent
Method for the hot swap of a mass storage adapter on a system including a statically loaded adapter driver
TL;DR: In this article, a software architecture for the hot add and swap of adapters is presented, which allows users to replace failed components, upgrade outdated components, and add new functionality, such as new network interfaces, disk interface adapters and storage, without impacting existing users.
Patent
Method for automatically reporting a system failure in a server
TL;DR: In this article, the authors present a failure reporting system for a server system which includes a controller which monitors the server system for system failures, and generates an event signal and failure information if a system failure is detected.
Patent
Method and apparatus for configuring a bus-to-bus bridge
TL;DR: In this paper, an information processing system includes a processor for processing information; a processor bus, a first expansion bus, and a host bridge for coupling the processor bus to the first expansion buses; a second expansion bus; a first bus bridge and a first storage device for storing a first set of configuration data for the plurality of I/O devices.
Patent
Three bus server architecture with a legacy PCI bus and mirrored I/O PCI buses
TL;DR: In this article, the authors describe a fault-tolerant computer system consisting of at least two mirrored circuits, at least three mirrored IO devices, a detection means and a re-route means.
Patent
Dynamic buffer allocation for a computer system
TL;DR: In this paper, a system for dynamically allocating buffers between components in a computer system is described, which uses matched sets of bi-directional buffers to control data flow between the processor and the computer bus.
References
More filters
Patent
Bus arbitration system and method
TL;DR: In this article, a bus arbitration system for data processing systems is presented, where the processor units and local memories are coupled through a local bus to their associated local memory, and a determination section of the bus arbitration module determines whether access is available over the system data bus or a local data bus.
Patent
Method of arbitration for buses operating at different speeds
TL;DR: In this paper, a bus adapter coupling a system bus and an I/O bus which operate at different speeds and contain a plurality of devices, a method by which an arbiter in the bus adapter prevents contention for ownership of both buses by a device on either of the buses.
Patent
Interface controller with first and second buffer storage area for receiving and transmitting data between I/O bus and high speed system bus
TL;DR: In this article, the I/O processors are enabled to differentiate between read and write buffer full conditions, thereby effectively increasing the bandwidth of the ICN bus, which can be used for buffering information units.
Patent
Multiprocessing system implemented with microprocessors
James R. Holden,John G. Valassis +1 more
TL;DR: In this article, a bus assigner in an electronic data processing system for selectively assigning access to a system bus to one of a plurality of microprocessors comprising a multiprocessing system is presented.
Patent
Buffer apparatus for controlling access requests among plural memories and plural accessing devices
TL;DR: In this paper, a plurality of access requests to devices to be accessed (e.g., memory banks) commonly used by the accessing devices in a data processing system are stored in the request buffer means.