Patent
Single clock CMOS logic circuit with selected threshold voltages
TLDR
In this article, a CMOS logic circuit with a basic CMOS shift register useful as a shift register or in sequential logic circuits is provided, where the use of a single input clock signal along with the reduced number of transistors is achieved by proper selection of threshold voltages of the transistors.Abstract:Â
A CMOS logic circuit having a basic CMOS shift register useful as a shift register or in sequential logic circuits is provided. The circuit has two inverters plus an output inverter and two transistors which are enabled by a clock signal to couple the inverters together. The use of a single input clock signal along with the reduced number of transistors is achieved by proper selection of threshold voltages of the transistors.read more
Citations
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Patent
Power converter circuitry and method
Kent Kernahan,John Carl Thomas +1 more
TL;DR: In this article, a control system and method for simultaneously regulating the operation of a plurality of different types of switching power converters is presented, where the system utilizes in regulating the sampled data and nonlinear feedback control loops.
Patent
Speed enhancement technique for CMOS circuits
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Patent
Dynamic logic having power-down mode with periodic clock refresh for a low-power graphics controller
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Flip-flop circuit
TL;DR: A flip-flop circuit includes a first switch for controlling passing of input data in response to a single clock signal, a first inverter for inverting the data passed through the first switch, a second inverter, a third inverter and a fourth inverter.
Patent
Monolithically integrable MOS-comparator circuit
TL;DR: In this paper, a monolithically integrable MOS-comparator has a capacitor, a signal input and a reference input of the comparator being alternatingly connected to the capacitor via respective first and second clock-controlled transfer transistors.
References
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Patent
Logic circuit for bistable D-dynamic flip-flops
TL;DR: In this article, a logic circuit for dynamic D-flip-flop includes five n-channel MOS transistors and five p-channel transistors, and it works correctly without any additional delay element or capacitor.
Patent
Capacitive means for controlling threshold voltages in insulated gate field effect transistor circuits
TL;DR: In this paper, the effect of excessive threshold voltages in insulated gate field effect transistor inverter-type circuits utilizes capacitor pull-up, where capacitors are selectively coupled from various phased voltage outputs of a multi-phase voltage supply to the driver-gate of various field effect transistors to provide increased voltage during voltage pulses of the phase involved.
Patent
Digital circuit for amplifying a signal
Ando Tetsuo,Yamazaki Hiroshi +1 more
TL;DR: In this article, the source-drain circuit of a MIS field effect transistor is connected between input and output terminals and the gate of such transistor is supplied with a first clock pulse during the occurrence of the input signal, and a semiconductor substrate of one conductivity type is connected to ground and has first and second diffusion regions formed therein with a relatively small interval between such regions and with the second diffusion region being in the floating state.
Patent
Field effect transistor information transfer circuit for use in storage register
Jury Vasilievich Tayakin,Vladimir Pavlovich Sidorenko,Alexandr Yakovlevich Sirota,Jury Vladimirovich Prokofiev,Alexandr Maximovich Kopytov +4 more
TL;DR: An output device of a metal-insulator-semiconductor transistor integrated circuit comprises, according to the invention, a penultimate stage, an output transistor, a clock pulse terminal and a separation pulse terminal as discussed by the authors.