Book ChapterDOI
Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI
Akashi Satoh,Sumio Morioka +1 more
- pp 48-62
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TLDR
In this paper, the authors designed compact and high-speed implementations of the KASUMI block cipher and compared several prototypes to existing designs in ASICs and FPGAs.Abstract:
The KASUMI block cipher and the confidentiality (f8) and integrity (f9) algorithms using KASUMI in feed back cipher modes have been standardized by the 3GPP. We designed compact and high-speed implementations and then compared several prototypes to existing designs in ASICs and FPGAs. Making good use of the nested structure of KASUMI, a lot of function blocks are shared and reused. The data paths of the f8 and f9 algorithms are merged using only one 64-bit selector. An extremely small size of 3.07 Kgates with a 288 Mbps throughput is obtained for a KASUMI core using a 0.13-µm CMOS standard cell library. Even simultaneously supporting both the f8 and f9 algorithms, the same throughput is achieved with 4.89 Kgates. The fastest design supporting the two algorithms achieves 1.6 Gbps with 8.27 Kgates.read more
Citations
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Journal ArticleDOI
A review of lightweight block ciphers
TL;DR: A survey of lightweight cryptographic algorithms, presenting recent advances in the field and identifying opportunities for future research is provided, examining lightweight implementations of symmetric-key block ciphers in hardware and software architectures.
Journal ArticleDOI
Lightweight Cryptography Algorithms for Resource-Constrained IoT Devices: A Review, Comparison and Research Opportunities
TL;DR: In this article, the authors have compared the existing algorithms in terms of implementation cost, hardware and software performances and attack resistance properties and discussed the demand and a direction for new research in the area of lightweight cryptography to optimize balance amongst cost, performance and security.
Proceedings ArticleDOI
High-speed hardware implementations of the KASUMI block cipher
TL;DR: Two architectures and efficient implementations of the 64-bit KASUMI block cipher are presented and the proposed implementations outperform any previous published KASumI implementations in terms of performance.
Book ChapterDOI
A Very Compact Hardware Implementation of the MISTY1 Block Cipher
TL;DR: This paper proposes compact hardware (H/W) implementation for the MISTY1 block cipher, which is an ISO/IEC18033 standard encryption algorithm, and proposes two new methods; reducing temporary registers for the FO function, and shortening the critical path for the FI function.
Patent
Method of designing optimum encryption function and optimized encryption apparatus in a mobile communication system
TL;DR: In this paper, a method of designing an optimum encryption algorithm and an optimized encryption apparatus is described. But the method is not applicable to the problem of finding the optimal ciphertext.
References
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Book ChapterDOI
New Block Encryption Algorithm MISTY
TL;DR: The software implementation of MISTY1 with eight rounds can encrypt a data stream in CBC mode at a speed of 20Mbps and 40Mbps on Pentium/100MHz and PA-7200/120MHz, respectively.
Book ChapterDOI
On the Hardware Implementation of the 3GPP Confidentiality and Integrity Algorithms
TL;DR: The design and implementation of the Confidentiality and Integrity algorithms, which have been standardized by the 3- rd Generation Partnership Project, use a modified version of the MISTY scheme, named KASUMI, as a basic cryptographic engine.