Patent
SOC with low power and performance modes
TLDR
In this paper, the clock circuit is coupled to produce a first clock signal when the SOC is in low power mode and a second clock signal in a performance mode, where the first clock signals are less accurate than the second clock signals.Abstract:
A system on a chip includes a processing module, ROM, RAM, and a clocking circuit. The clock circuit is coupled to produce a first clock signal when the SOC is in a low power mode and to produce a second clock signal when the SOC is in a performance mode, where the first clock signal is less accurate than the second clock signal. The clock circuit consumes more power when producing the second clock signal than when producing the first clock signal.read more
Citations
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Patent
Thread optimized multiprocessor architecture
TL;DR: In this paper, the authors present a system consisting of a plurality of parallel processors on a single chip, and a computer memory located on the chip and accessible by each of the processors.
Patent
Microprocessor having a secure execution mode with provisions for monitoring, indicating, and managing security levels
G. Glenn Henry,Terry Parks +1 more
TL;DR: In this paper, a watchdog manager monitors environments of the microprocessor by noting and evaluating data communicated by a plurality of monitors, and classifies the data to indicate a security level associated with execution of the secure application program, and that directs secure execution mode logic to perform responsive actions in accordance with the security level.
Patent
On-die cryptographic apparatus in a secure microprocessor
G. Glenn Henry,Terry Parks +1 more
TL;DR: In this article, a secure non-volatile memory and a microprocessor are coupled via a private bus and a system memory via a system bus, respectively, for secure execution.
Patent
Termination of secure execution mode in a microprocessor providing for execution of secure code
G. Glenn Henry,Terry Parks +1 more
Abstract: An apparatus providing for a secure execution environment including a microprocessor and a secure non-volatile memory. The microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The microprocessor has secure execution mode logic that is configured to detect execution of a secure execution mode return event, and that is configured to terminate a secure execution mode within the microprocessor, where the secure execution mode exclusively supports execution of the secure application program. The secure non-volatile memory is coupled to the microprocessor via a private bus and is configured to store the secure application program prior to termination of the secure execution mode, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.
Patent
Microprocessor apparatus for secure on-die real-time clock
G. Glenn Henry,Terry Parks +1 more
TL;DR: In this paper, an external crystal is coupled to a secure real-time clock within a microprocessor and is configured to cause an oscillator within the secure real time clock to generate an oscillating output voltage that is proportional to the frequency of the external crystal.
References
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Patent
High performance microprocessor having variable speed system clock
Charles H. Moore,Russell H. Fish +1 more
TL;DR: In this article, a high performance, low cost microprocessor system having a variable speed system clock is described, which includes an integrated circuit having a central processing unit and a ring oscillator VSS system clock for clocking the microprocessor.
Patent
Monolithic Clock Generator and Timing/Frequency Reference
TL;DR: In this paper, the authors provide a clock generator and/or a timing and frequency reference, with multiple operating modes, such as power conservation, clock, reference, and pulsed modes.
Patent
Dual-processor complex domain floating-point dsp system on chip
Pierluigi Paolucci,Benedetto Altieri,F. Aglietti,Piergiovanni Bazzana,Antonio Cerruto,M. Cosimi,A. Michelotti,Elena Pastorelli,Andrea Ricciardi +8 more
TL;DR: In this article, a system for digital signal processing, configured as a system on chip (SoC) (102), combines a microprocessor core (106) and digital signal processor (DSP) core (108) with floating-point data processing capability.
Patent
Dual bandgap voltage reference system and method for reducing current consumption during a standby mode of operation and for providing reference stability during an active mode of operation
TL;DR: In this paper, a method of operating a memory includes generating a first reference voltage and detecting an active mode of operation of the memory by charging a node to develop a second reference voltage having a desired value on the node.
Patent
Systems and Methods for Operational Power Management
TL;DR: In this article, a synchronous semiconductor circuit with two or more clock sources and a power management controller is presented, where the power management controllers are operable to apply power to one of the clock sources, and then select another of the sources for synchronization of the circuit.