Patent
Substrate structure of semiconductor device and method of manufacturing the same
TLDR
In this paper, an element region, the element isolating region and the field oxide region on the silicon substrate are formed substantially flat, and a silicon oxide insulating film is formed on the inner wall of the groove.Abstract:
A substrate structure utilized to fabricate a semiconductor device is constituted by a silicon substrate; an element region selectively formed on the silicon substrate and a relatively thick field oxide region formed adjacent to the element region; an element isolating region formed between the element region and the field oxide region, the element isolating region being in direct contact with the field oxide region; the element isolating region being provided with a relatively deep groove formed in the silicon substrate and having a relatively small width; a silicon oxide insulating film formed on the inner wall of the groove; and a silicon nitride insulating film disposed on the silicon oxide insulating film. The surfaces of the element region, the element isolating region and the field oxide region on the silicon substrate are formed substantially flat.read more
Citations
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Patent
A dram cell formed on an insulating layer having a buried semiconductor pillar structure and a manufacturing method thereof
TL;DR: In this paper, a DRAM cell structure and a manufacturing method for DRAM cells is described, in which a transistor and a capacitor are formed three-dimensionalally in an SOI structure.
Patent
Process of forming an isolation structure
TL;DR: In this paper, two thin wedges of oxide extending along and from the boundaries of the field oxide layer without solution of continuity inside the substrate are obtained by means of deep anisotropic etch of silicon through a suitably exposed area, for example by an overetch of the nitride used for growing the thick oxide layer according to the known technique and by the subsequent filling of the deep etch with thermally grown silicon oxide.
Patent
Alignment mark system for electron beam/optical mixed lithography
TL;DR: In this paper, a system for making alignment marks in a semiconductor for a wafer etched in alignment with and bordered by an isolation level oxide was proposed. But the alignment marks were not defined.
Patent
Trench isolation process and structure
Robert J. Mattox,Steven Fong +1 more
TL;DR: In this article, a structure and method for forming an isolation wall in an etched trench are described, where the trench walls are covered by a thin silicon oxide layer and the trench conformally filled with an oxy-nitride mixture having a particular range of composition.
Patent
Method of fabricating a semiconductor device
TL;DR: In this article, the trench isolation technique was used for the fabrication of wide element isolation regions in submicron semiconductor devices, where the entire wide-element isolation region is covered with an insulating material.
References
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Patent
Total dielectric isolation for integrated circuits
TL;DR: In this article, a fully isolated dielectric structure for isolating regions of monocrystalline silicon from one another and method for making such structure are described; the structure uses a combination of recessed oxide isolation with pairs of parallel, anisotropic etched trenches which are subsequently oxidized and filled to give complete isolateric isolation for regions of mono-silicon.
Patent
Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking
TL;DR: The lateral intradevice isolation as discussed by the authors enables the simultaneous formation through a single mask of an active region and a contact region for a different active region both on the same planar surface of a semiconductor substrate.
Patent
Method for fabricating isolation region in semiconductor devices
Hiroshi Goto,Akira Tabata +1 more
TL;DR: In this paper, a sharp-edged isolation groove having a U-shaped cross-section is made by reactive ion etching, and the inner surface of the isolation groove is coated by an insulating film.
Patent
Method of fabricating narrow deep grooves in silicon
TL;DR: In this article, a method of fabricating deep grooves having submicron widths in a semiconductor substrate is described, which is used to provide deep dielectric isolation between active areas in high density integrated circuits.