UC Irvine
ICS Technical Reports
Title
Survey of switching techniques in high-speed networks and their performance
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https://escholarship.org/uc/item/6r54g1n5
Authors
Oie, Yuji
Suda, Tatsuya
Kolson, David
et al.
Publication Date
1989-10-12
Peer reviewed
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L~w
(Title
17
u_s.c.)
_SURVEY
OF
SWITCHING
TECHNIQUES
IN
HIGH-SPEED
NETWORKS
AND
THEIR
PERFORMANC~
Yuji OIE
Tatsuya
SUDA
David KOLSON
Masayuki MURATA
Hideo MIYAHARA
Technical Report
No.
89-37
Department
of
Information and Computer Science
University of California, Irvine
Irvine, California 92717
§urvey
of
Switching
Techniques
in
High-Speed
Networks
and
Their
Performance*
Yuji
Or~;,
Tatsuya
SUDA
2
,
David KOLSON
2
,
Masayuki MURATA
3
,
Hideo MIYAHARA
3
r
.,,.
October
12,
1989
1.
Department of Electrical Engineering, Sasebo College of Technology, Sasebo 857-11,
Japan.
2.
Department
of
Information
and
Computer
Science,
University
of
Califor-
nia,
Irvine,
CA
92717,
U.S.A.
3.
Department of Information
and
Computer Sciences, Faculty of Engineering Science,
Osaka University, Toyonaka 560, Japan.
Mailing
Address:
All
the
future correspondence should be addressed
to
Tatsuya
Suda
at
the above
address.
* .
This material is based upon work supported by the National Science Foundation
under Grant
No.
D CI-8602052. This research
is
also in
part
supported by the
University of California
MICRO program.
Abstract
One of
the
most promising approaches for high speed networks for integrated service
applications is fast packet switching, or ATM (Asynchronous Transfer Mode).
AT~!
can
be characterized by very high speed transmission links
and
simple,
hard
wired protocols
within a network. To
match
the
transmission speed of
the
network links,
and
to minimize
the
overhead due to
the
processing of network protocols,
the
switching of cells
is
done in
hardware
switching fabrics in ATM networks.
A
number
of designs has been proposed for implementing ATM switches. While many
differences exist among
the
proposals,
the
vast
majority
of
them
is based on self-routing
multi-stage interconnection networks.
This
is
because of
the
desirable features of multi-
stage interconnection networks such as self-routing capability
and
suitability
for VLSI
implementation.
Existing ATM switch architectures
can
be
classified
into
two
major
classes: blocking
switches, where blackings of cells
may
occur within a switch when more
than
one cell
contends for
the
same
internal
link,
and
non-blocking switches, where no internal blocking
occurs. A large
number
of techniques has also been proposed
to
improve
the
performance
of blocking
and
nonblocking switches. In this
paper,
we
present
an
extensive survey of
the
existing proposals for ATM switch architectures, focusing on
their
performance issues.
1
