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Synchronizing processors through memory requests in a tightly coupled multiprocessor

André Seznec, +1 more
- Vol. 16, Iss: 2, pp 393-400
TLDR
The GREEDY network is presented, a new interconnection network (IN) for tightly coupled multiprocessors (TCMs) and an original and cost effective hardware synchronization mechanism is proposed which may be achieved at execution time on a very large spectrum of loops.
Abstract: 
To satisfy the growing need for computing power, a high degree of parallelism will be necessary in future supercomputers. Up to the late 70s, supercomputers were either multiprocessors (SIMD-MIMD) or pipelined monoprocessors. Current commercial products combine these two levels of parallelism.Effective performance will depend on the spectrum of algorithms which is actually run in parallel. In a previous paper [Je86], we have presented the DSPA processor, a pipeline processor which is actually performant on a very large family of loops.In this paper, we present the GREEDY network, a new interconnection network (IN) for tightly coupled multiprocessors (TCMs). Then we propose an original and cost effective hardware synchronization mechanism. When DSPA processors are connected with a shared memory through a GREEDY network and synchronized by our synchronization mechanism, a very high parallelism may be achieved at execution time on a very large spectrum of loops including loops where independency of the successive iterations cannot be checked at compile time as e.g. loop 1: DO 1 I=1 N1 A(P(I)=A(Q(I))

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HAL Id: inria-00075790
https://hal.inria.fr/inria-00075790
Submitted on 24 May 2006
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Synchronizing processors through memory requests in a
tightly coupled multiprocessor
André Seznec, Yvon Jégou
To cite this version:
André Seznec, Yvon Jégou. Synchronizing processors through memory requests in a tightly coupled
multiprocessor. [Research Report] RR-0762, INRIA. 1987. �inria-00075790�
Citations
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Patent

Cluster architecture for a highly parallel scalar/vector multiprocessor system

Steve S. Chen, +6 more
TL;DR: A cluster architecture for a highly parallel multiprocessor computer processing system as mentioned in this paper is comprised of one or more clusters of tightly-coupled, high-speed processors capable of both vector and scalar parallel processing.
Proceedings ArticleDOI

Characterizing the behavior of sparse algorithms on caches

Olivier Temam, +1 more
TL;DR: The behavior on cache of one of the most frequent primitives, SpMxV sparse matrix vector multiply, is analyzed and a blocking technique which takes into account the specifics of sparse codes is proposed.
Patent

Interleaved memory access system having variable-sized segments logical address spaces and means for dividing/mapping physical address into higher and lower order addresses

Steve S. Chen, +6 more
TL;DR: In this paper, a method of accessing common memory in a cluster architecture for a highly parallel multiprocessor scaler/factor computer system using a plurality of segment registers in which a logical address is within a start and end range as defined by the segment registers and then relocating the logical address to a physical address using a displacement value in another segment register.
Proceedings ArticleDOI

GTS: parallelization and vectorization of tight recurrences

Eduard Ayguadé, +3 more
TL;DR: A new method for extracting the maximum parallelism or vector operations out of DO loops with tight recurrences using sequential programming languages, devised to produce code for shared memory multiprocessors or vector machines.
Proceedings ArticleDOI

The design of a high-performance scalable architecture for image processing applications

C.T. Gray, +3 more
TL;DR: The authors present the organization of an interleaved wrap-around memory system for a partitionable parallel/pipeline architecture with P pipes of L processors each, designed to efficiently support real-time image processing and computer vision algorithms, especially those requiring global data operations.
References
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Journal ArticleDOI

Access and Alignment of Data in an Array Processor

D.H. Lawrie
- 01 Dec 1975 - 
TL;DR: This paper discusses the design of a primary memory system for an array processor which allows parallel, conflict-free access to various slices of data, and subsequent alignment of these data for processing, and a network based on Stone's shuffle-exchange operation is presented.
Journal ArticleDOI

The NYU Ultracomputer—Designing an MIMD Shared Memory Parallel Computer

Gottlieb, +4 more
- 01 Feb 1983 - 
TL;DR: The design for the NYU Ultracomputer is presented, a shared-memory MIMD parallel machine composed of thousands of autonomous processing elements that uses an enhanced message switching network with the geometry of an Omega-network to approximate the ideal behavior of Schwartz's paracomputers model of computation.
Proceedings Article

The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture.

Gregory Francis Pfister, +8 more
Journal ArticleDOI

The Organization and Use of Parallel Memories

Paul Budnik, +1 more
- 01 Dec 1971 - 
TL;DR: As computer CPUs get faster, primary memories tend to be organized in parallel banks, and important questions of design and use of such memories are discussed.
Proceedings Article

Doacross: Beyond Vectorization for Multiprocessors.

Ron K. Cytron