Journal ArticleDOI
Synthesis and optimization of image processing accelerators using domain knowledge
Oliver Reiche,Konrad Haublein,Marc Reichenbach,Moritz Schmid,Frank Hannig,Jürgen Teich,Dietmar Fey +6 more
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TLDR
The resulting FPGA accelerators are compared to highly optimized Graphics Processing Unit (GPU) implementations of several image filters relevant for close-to-sensor image and video processing with stringent real-time constraints, such as in the automotive domain.About:
This article is published in Journal of Systems Architecture.The article was published on 2015-11-01. It has received 8 citations till now. The article focuses on the topics: Image processing & VHDL.read more
Citations
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Journal ArticleDOI
An Evaluation of a High-Level Synthesis Approach to the FPGA-Based Submicrosecond Real-Time Simulation of Power Converters
TL;DR: This paper evaluates the benefits of using a high-level synthesis tool to develop field-programmable gate array (FPGA)-based real-time simulators for power electronics systems and shows that HLS can be used for hardware-in-the-loop (HIL) applications when the circuit to be simulated is small and the target clock frequency is not too high.
Proceedings ArticleDOI
Generating FPGA-based image processing accelerators with Hipacc: (Invited paper)
TL;DR: In this paper, the Hipacc framework, a DSL and source-to-source compiler for image processing, is presented, where domain knowledge can be captured to generate tailored implementations for C-based HLS from a common high-level DSL description targeting FPGAs.
Journal ArticleDOI
Grey Wolf optimization based Artificial Neural Network for Classification of Kidney Images
TL;DR: This study proposes Grey Level Co-occurrence Matrix-based Probabilistic Principal Component Analysis (PPCA) and Artificial Neural Network (ANN) method for the classification of kidney images and the analyzed result produces 98% accuracy using GWO-FFBN technique.
Journal ArticleDOI
Oppositional Gravitational Search Algorithm and Artificial Neural Network-based Classification of Kidney Images
TL;DR: This research effectively classify normal and abnormal kidney images through US based on the selection of relevant features through gray-scale conversion, region-of-interest generation, multi-scale wavelet-based Gabor feature extraction, probabilistic principal component analysis-based feature selection and adaptive artificial neural network technique.
Journal ArticleDOI
A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators
TL;DR: The proposed overlays are parametrizable in size, they are cost-effective, they provide sub-microsecond time-steps, and they offer a high computational performance with a reported peak performance of 300 GFLOPS.
References
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Journal ArticleDOI
Distributed embedded smart cameras for surveillance applications
TL;DR: This work designed the smart camera as a fully embedded system, focusing on power consumption, QoS management, and limited resources, and combined several smart cameras to form a distributed embedded surveillance system that supports cooperation and communication among cameras.
Journal ArticleDOI
Smart cameras as embedded systems
Wayne Wolf,B. Ozer,Tiehan Lv +2 more
TL;DR: In this paper, the authors developed a first-generation smart camera system that can detect people and analyze their movement in real-time, which is a leading edge application for embedded system research.
Journal ArticleDOI
Decoupling algorithms from schedules for easy optimization of image processing pipelines
TL;DR: This work proposes a representation for feed-forward imaging pipelines that separates the algorithm from its schedule, enabling high-performance without sacrificing code clarity, and demonstrates the power of this representation by expressing a range of recent image processing applications in an embedded domain specific language called Halide and compiling them for ARM, x86, and GPUs.
Proceedings ArticleDOI
Designing Modular Hardware Accelerators in C with ROCCC 2.0
TL;DR: A major revision to the Riverside Optimizing Compiler for Configurable Circuits (ROCCC), designed to create hardware accelerators from C programs, with novel additions including an intuitive modular bottom-up design of circuits from C, and separation of code generation from specific FPGA platforms.