Patent
System and method for simulating discrete functions using ordered decision arrays
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TLDR
In this article, a data structure that completely and accurately models a system of discrete function elements is presented, and a discrete function simulator is used to simulate the system using the data structure.Abstract:
A system and method increases discrete function simulator performance by creating a data structure that completely and accurately models a system of discrete function elements. A discrete function simulator simulates the system using the data structure. Sequential circuits are converted into blocks of combinational elements having latch variables stored to and read from memory. The simulator performance is dependent upon the number of system inputs and outputs and not on the number of discrete function elements in the circuit being simulated.read more
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References
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Proceedings ArticleDOI
Dynamic variable ordering for ordered binary decision diagrams
TL;DR: Experiments with dynamic variable ordering on the problem of forming the OBDD's for the primary outputs of a combinational circuit show that many computations complete using dynamicVariable ordering when the same computation fails otherwise.
Patent
Simulation model generation from a physical data base of a combinatorial circuit
Nim C. Lam,Amrit K. Lalchandani +1 more
TL;DR: In this article, a design layout sequence for an application specific integrated circuit such as an ECL gate array is simulated after both schematic capture and placement and routing using a library containing simulation models for each type of macrocell used in the design, and the resulting set of Boolean equations is used to construct the gate-level netlist that is incorporated into the simulation model of the macrocell.
Patent
Simulation of selected logic circuit designs
Abstract: A system and method for selectively simulating logic circuit designs in which a data tables generator receives information from a schematic entry program or netlist entry file and produces data tables for use by a simulator. A designer provides inputs to the data tables generator from a schematic entry program or a netlist entry file. The data tables generator generates from the information received a table of used integrated circuits and a table of their connections. A simulator then receives the output from the data tables generator and produces a design simulation program table that executes integrated circuit model subroutine stored in an integrated circuit model reference library and netlist subroutines stored in a netlist connectivity table. The system may also be used for testing logic circuits on a printed circuit board by capturing signals from a potentially defective logic section of the printed circuit board and feeding them into test points of the integrated circuit simulated by the computer simulator.
Proceedings ArticleDOI
Fast discrete function evaluation using decision diagrams
Patrick C. McGeer,Kenneth L. McMillan,Alexander Saldanha,Alberto Sangiovanni-Vincentelli,Patrick Scaglia +4 more
TL;DR: An approach for fast discrete function evaluation based on multi-valued decision diagrams (MDD) based on decision-diagram based function evaluation offers orders-of-magnitude potential speedup over traditional logic simulation methods.
Patent
Hierarchical netlist extraction tool
TL;DR: In this article, a general netlist extraction tool which generates tool-specific incremental and hierarchical netlist extractors is presented. But this tool requires a large number of schematics.