Patent
Test method and structure for integrated circuits before complete metalization
Janakiraman Viraraghavan,Ramesh Raghavan,Balaji Jayaraman,Thejas Kempanna,Rajesh R. Tummuru,Toshiaki Kirihata +5 more
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TLDR
In this paper, the authors present methods and test structures for an intermediate metal level of an integrated circuit (IC), which is one of a plurality of metal levels in the IC structure other than a capping metal level.Abstract:
Aspects of the present disclosure include methods and test structures for an intermediate metal level of an integrated circuit (IC). A method according to the present disclosure can include: fabricating a first plurality of metal levels including an intermediate metal level of an IC structure, the intermediate metal level being one of a plurality of metal levels in the IC structure other than a capping metal level of the IC structure; performing a first functional test on a first circuit positioned within the intermediate metal level; fabricating a second plurality of metal levels after performing the first functional test, the second plurality of metal levels including the capping metal level of the IC structure; and performing a second functional test on a second circuit positioned within the plurality of metal levels, after the fabricating of the capping metal level.read more
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Multilayer back end of line (BEOL)-stackable cross-point memory array with complementary pass transistor selectors
TL;DR: In this article, a multilayer cross point memory array with parallel-connected field effect selection transistors is presented, in which the gate of the p-FET and the gate in an adjacent stack are connected to the same word line.
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Patent
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Patent
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Patent
Semiconductor integrated circuit device with test element group circuit
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