The Cell Matrix: an architecture for nanocomputing

TLDR: The construction of physically homogeneous, undifferentiated hardware that is later, after manufacture, differentiated into various digital circuits achieves both the immediate goal of achieving specific CPU and memory architectures using atomic-scale switches as well as the larger goal of being able to construct any digital circuit, using the same fixed manufacturing process.

Abstract: Much effort has been put into the development of atomic-scale switches and the construction of computers from atomic-scale components. We propose the construction of physically homogeneous, undifferentiated hardware that is later, after manufacture, differentiated into various digital circuits. This achieves both the immediate goal of achieving specific CPU and memory architectures using atomic-scale switches as well as the larger goal of being able to construct any digital circuit, using the same fixed manufacturing process. Moreover, this opens the way to implementing fundamentally new types of circuit, including dynamic, massively parallel, self-modifying ones. Additionally, the specific architecture in question is not particularly complex, making it easier to construct than most other architectures. We have developed a computing architecture, the Cell MatrixTM, that fits this more attainable manufacturing goal, as well as a process for taking undifferentiated hardware and differentiating it efficiently and cheaply into desirable circuitry. The Cell Matrix is based on a single atomic unit called a cell, which is repeated over and over to form a multidimensional matrix of cells. In addition to being general purpose, the architecture is highly scalable, so much so that it appears to provide access to the differentiation and use of trillion trillion switch hardware. This is not possible with a field programmable gate array architecture, because its gate array is configured serially, and serial configuration of trillion trillion switch hardware would take years. This paper describes the cell in detail and describes how networks of cells in a matrix are used to create small circuits. It also describes a sample application of the architecture that makes beneficial use of high switch counts.