A possible design alternative for improving the performance of a multiprocessor system is to insert a private cache between each processor and the shared memory. The caches act as high-speed buffers by reducing the effective memory access time, and affect the delays caused by memory conflicts. In this paper, we study the effectiveness of caches in a multiprocessor system. The shared memory is pipelined and interleaved to improve the block transfer rate, and it assumes a two-dimensional organization, previously studied under random and word access. An approximate model is developed to estimate the processor utilization and the speed-up improvement provided by the caches.

The Effectiveness of cache Memories in a Multiprocessor Environment.

Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories

The years since the advent of multiprocessing have witnessed the proliferation of journal articles, conferences, and symposia on multiprocessing systems and closely related topics. The body of literature so generated is both vast and scattered–a situation that can be quite disheartening to one unfamiliar with this area of computer science.

The Effectiveness of cache Memories in a Multiprocessor Environment.

Citations

Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories

Multiprocessing: An Annotated Bibliography

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