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Journal ArticleDOI

The Gamma Network

TLDR
A detailed terminal reliability analysis of the Gamma network is performed, deriving expressions for the reliability between an input and output terminal and the permuting capabilities of the gamma network.
Abstract
The Gamma network is an interconnection network connecting N = 2n inputs to N outputs. It is a multistage network with N switches per stage, each of which is a 3 input, 3 output crossbar. The stages are linked via "power of two" and identify connections in such a way that redundant paths exist between the input and output terminals. In this network, a path from a source to a destination may be represented using one of the redundant forms of the difference between the source and destination numbers. The redundancy in paths may thus be studied using the theory of redundant number systems. Results are obtained on the distribution of paths connecting inputs and outputs, and the permuting capabilities of the Gamma network. Frequently used permutations and control mechanisms are discussed briefly. We also perform a detailed terminal reliability analysis of the Gamma network, deriving expressions for the reliability between an input and output terminal.

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Citations
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Journal ArticleDOI

Performance analysis of multibuffered packet-switching networks in multiprocessor systems

TL;DR: In this paper, an analytic model and analytic results for the performance of multibuffered packet-switching interconnection networks in multiprocessor systems are presented and compared to simulation results.
Journal ArticleDOI

The Gamma network: A multiprocessor interconnection network with redundant paths

TL;DR: The Gamma network is an interconnection network connecting N&equil;2" inputs to N outputs that may be represented using one of the redundant forms of the difference between the source and destination numbers.
Journal ArticleDOI

The extra stage Gamma network

TL;DR: It is shown that the extra stage of 0, +1, -1 connection patterns gives the most uniform distribution, and also results in a 1-fault tolerant interconnection network.
Journal ArticleDOI

Fault-Tolerant Multiprocessors with Redundant-Path Interconnection Networks

TL;DR: This paper first formulate the problem of performing an arbitrary permutation on the fault-free network as a vertex-coloring problem and later extend this to networks with noncritical faults, and considers the class of BPC (bit permute-complement) permutations: algorithms for performing arbitrary permutations in this class on the extra-stage delta network are given.
Journal ArticleDOI

Redundant paths and reliability bounds in gamma networks

TL;DR: Reliability of an MIN is used as a measure of system’s ability to transform information from input to output devices, and reliability bounds to estimate the exact reliability of a gamma network are proposed.
References
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Journal ArticleDOI

Signed-Digit Numbe Representations for Fast Parallel Arithmetic

TL;DR: Sign-digit representations limit carry-propagation to one position to the left during the operations of addition and subtraction in digital computers and arithmetic operations with signed-digit numbers: addition, subtraction, multiplication, division and roundoff are discussed.
Journal ArticleDOI

Access and Alignment of Data in an Array Processor

TL;DR: This paper discusses the design of a primary memory system for an array processor which allows parallel, conflict-free access to various slices of data, and subsequent alignment of these data for processing, and a network based on Stone's shuffle-exchange operation is presented.
Journal ArticleDOI

The Indirect Binary n-Cube Microprocessor Array

TL;DR: This paper explores the possibility of using a large-scale array of microprocessors as a computational facility for the execution of massive numerical computations with a high degree of parallelism.
Proceedings ArticleDOI

Banyan networks for partitioning multiprocessor systems

TL;DR: Results will be given indicating that a cost/performance advantage over the crossbar can be obtained for large systems and that the cross bar can, in fact, be considered a non-optimal special case of a banyan network.
Journal ArticleDOI

The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems

TL;DR: It is shown that the ESC provides fault tolerance for any single failure, and the network can be controlled even when it has a failure, using a simple modification of a routing tag scheme proposed for the Generalized Cube.
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