scispace - formally typeset
Journal ArticleDOI

Signed-Digit Numbe Representations for Fast Parallel Arithmetic

Reads0
Chats0
TLDR
Sign-digit representations limit carry-propagation to one position to the left during the operations of addition and subtraction in digital computers and arithmetic operations with signed-digit numbers: addition, subtraction, multiplication, division and roundoff are discussed.
Abstract
This paper describes a class of number representations which are called signed-digit representations. Signed-digit representations limit carry-propagation to one position to the left during the operations of addition and subtraction in digital computers. Carry-propagation chains are eliminated by the use of redundant representations for the operands. Redundancy in the number representation allows a method of fast addition and subtraction in which each sum (or difference) digit is the function only of the digits in two adjacent digital positions of the operands. The addition time for signed-digit numbers of any length is equal to the addition time for two digits. The paper discusses the properties of signed-digit representations and arithmetic operations with signed-digit numbers: addition, subtraction, multiplication, division and roundoff. A brief discussion of logical design problems for a signed-digit adder concludes the presentation.

read more

Citations
More filters
Book

Digital arithmetic

TL;DR: Digital Arithmetic, two of the field's leading experts, deliver a unified treatment of digital arithmetic, tying underlying theory to design practice in a technology-independent manner, to develop sound solutions, avoid known mistakes, and repeat successful design decisions.
Journal ArticleDOI

Use of minimum-adder multiplier blocks in FIR digital filters

TL;DR: Three new algorithms for the design of multiplier blocks are described: an efficient modification to an existing algorithm, a new algorithm giving better results, and a hybrid of these two which trades off performance against computation time.
Journal ArticleDOI

An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients

TL;DR: In this paper, an improved algorithm is presented for the discrete optimization of finite-impulse response (FIR) digital filter coefficients which are represented by a canonic signed-digit (CSD) code, i.e., numbers representable as sums or differences of powers of two.
Journal ArticleDOI

Multiplierless multiple constant multiplication

TL;DR: This work proposes a new algorithm for the multiple constant multiplication problem, which produces solutions that require up to 20% less additions and subtractions than the best previously known algorithm and can handle problem sizes as large as 100 32-bit constants in a time acceptable for most applications.
Journal ArticleDOI

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

TL;DR: Since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation and is excellent in both computation speed and regularity in layout.
References
More filters
Journal ArticleDOI

A New Class of Digital Division Methods

TL;DR: A class of division methods best suited for use in digital computers with facilities for floating point arithmetic by considering the nature of each quotient digit as generated during the division process is described.