Patent
Time multiplexed bus matrix switching system
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TLDR
In this article, a clock synchronized time division switches are connected respectively to the input signal lines, bus highways, and the output signal lines in a multihop system, and each one is controlled by its own storage of selected addresses in time slot order.Abstract:
Ports including at least input and output signal lines are collected into port groups. For each port group three separate clock synchronized time division switches are connected respectively to the input signal lines, bus highways and the output signal lines. All time division switches of the system are synchronized by a system clock and each one is controlled by its own storage of selected addresses in time slot order. A plurality of bus highways is provided and the input time division switch connects signals to a specific bus highway of the system. A second time division switch selects the bus highway for connection to the output section of the port group. A third time division switch selects the output port to which the selected bus highway is connected. In one embodiment the bus highways directly connect the port groups. In another, a central inter-connect matrix is provided to make the connection between the first and second time division switches.read more
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References
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TL;DR: In this paper, the authors proposed an adaptive sampling scheme for increasing the channel capacity of a fixed bandwidth communication link by reducing the redundancy characteristic of nonadaptive systems, where the transmitter allocates space in a fixed bit length sample field among multiple channels on a frame by frame basis.
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