Topology generation process for automated circuit design

TLDR: In this paper, a process automatically generates topology data for fabricating large scale integrated circuits is described, where technology data, a logic function description and logic circuit components are generated and input to a data processing system together with geometric dimension data descriptive of the basic elements of the logic circuits components.

Abstract: A process automatically generating topology data for fabricating large scale integrated circuits. Technology data (110), a logic function description and logic circuit components (120) are generated and input to a data processing system together with geometric dimension data descriptive of the basic elements of the logic circuit components (170). The geometric dimension data is assembled into a plurality of intermediate level geometric topology patterns under control of the logic function description and the intermediate level geometric topology patterns are assembled into a prime level geometric topology representative of the logic function description (200). The logic circuit components are merged with the prime level geometric topology (500) to produce a grid array to be fabricated into a large scale integrated circuit.