Patent
Zero setup time flip flop
TLDR
In this paper, a storage element having a data input terminal, a clock input terminal and a data output terminal is described, which is able to capture a logic value of a data signal on the input terminal with substantially zero setup time at an active edge of a clock signal.Abstract:
Circuits and methods for a zero setup time storage element are disclosed. A storage element having a data input terminal, a clock input terminal and a data output terminal is able to capture a logic value of a data signal on the data input terminal with a substantially zero setup time at an active edge of a clock signal. Furthermore, some embodiments of the storage element are able to drive the captured logic value until the next active edge. One embodiment of the storage element includes a control circuit coupled to an output driver circuit. Depending on the state of the data input signal during an active edge, the control circuit can drives a first control signal to the output driver circuit or a second control signal to the output driver circuit. The output driver drives a data output signal on the data output terminal of the storage element based on the values of the control signals.read more
Citations
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References
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Patent
Flip-flop circuit
Hiroki Yamashita,Hiroyuki Itoh,Hirotoshi Tanaka,Atsumi Kawata,Kenji Nagai,Kazuhiro Yoshihara,Ichiro Imaizumi +6 more
TL;DR: In this article, a flip-flop circuit receives a pair of complementary data signals, then outputs complementary signals corresponding to the pair of data signals to a driving gate means which outputs a signal corresponding to at least one data signal.
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