How to build an all-digital PLL for clock synthesis?
Best insight from top research papers
To build an all-digital PLL for clock synthesis, a few methods have been proposed in the literature. One approach is to use a fully synthesizable description of a digital controlled oscillator (DCO) with a variable length ring oscillator (VLRO) as the coarse part and a fine-tune unit based on a path selector of different pin-to-pin delays in a NAND standard cell . Another method involves using a self-calibrated hierarchical Time to Digital Converter (TDC) in the ADPLL design, along with two digitally controlled oscillators to cover a wide range of frequencies . Additionally, a discrete-time framework based on nonlinear stochastic iterating maps has been proposed for modeling and studying ADPLL networks, allowing for the optimization of control parameters and synchronization in frequency and phase . Furthermore, an ADPLL utilizing the successive approximation (SAR) algorithm has been presented, which includes a high-frequency resolution digitally controlled oscillator, a time-to-digital converter, a frequency detection divider, and a SAR controller . Mathematical models have also been derived for ADPLLs employing time-to-digital phase detectors, providing benefits for simulation and design .
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| Papers (4) | Insight |
|---|---|
26 Jun 2016 | The paper provides a mathematical model of an All-Digital Phase-Locked Loop (ADPLL) for clock synthesis. It compares the model with a behavioral model implemented in MATLAB Simulink and experimental measurements of a 65nm CMOS ADPLL, showing good agreement. |
01 Dec 2018 | The paper provides a proposal for an all-digital PLL with a self-calibrated hierarchical Time to Digital Converter (TDC) and two digitally controlled oscillators to cover a wide frequency range. However, it does not provide a detailed step-by-step guide on how to build an all-digital PLL for clock synthesis. |
01 Oct 2016 2 Citations | The paper presents an all-digital PLL (ADPLL) for clock synthesis using a successive approximation (SAR) algorithm. The ADPLL consists of a digitally controlled oscillator, a time-to-digital converter, a frequency detection divider, and a SAR controller. |
26 Jan 2021 | The paper provides a method for building an all-digital phase-locked loop (ADPLL) for clock synthesis using standard cells and a time to digital converter (TDC) circuit. |
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