Showing papers on "Bit plane published in 2009"

Pair Bit Line Programming To Improve Boost Voltage Clamping

Abstract: A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.

Frame Selected Approach for Hiding Data within MPEG Video Using Bit Plane Complexity Segmentation

Abstract: Bit Plane Complexity Segmentation (BPCS) digital picture steganography is a technique to hide data inside an image file. BPCS achieves high embedding rates with low distortion based on the theory that noise-like regions in an image's bit-planes can be replaced with noise-like secret data without significant loss in image quality. . In this framework we will propose a collaborate approach for select frame for Hiding Data within MPEG Video Using Bit Plane Complexity Segmentation. This approach will invent high secure data hidden using select frame form MPEG Video and furthermore we will assign the well-built of the approach; during this review the author will answer the question why they used select frame steganography. In additional to the security issues we will use the digital video as a cover to the data hidden. The reason behind opt the video cover in this approach is the huge amount of single frames image per sec which in turn overcome the problem of the data hiding quantity, as the experiment result shows the success of the hidden data within select frame, extract data from the frames sequence. These function without affecting the quality of the video.

Truncated graycoded bit-plane matching based motion estimation and its hardware architecture

Abstract: This paper proposes an efficient low bit-depth representation based motion estimation approach which is particularly suitable for low-power consumer electronics devices. In the proposed approach motion estimation is carried out using bit truncated gray-coded image pixels. The corresponding hardware architecture is also designed and presented in this paper to show the effectiveness of the proposed approach. It is shown that the proposed approach provides improved motion estimation accuracy compared to conventional bit-truncation based approaches that are directly applied to binary coded pixel values. The proposed approach uses simple Gray-coding, that has very low-complexity and can be applied on a pixel-by-pixel basis. Hence, the comparatively more complex transformation processes required in one bit-transform or two-bit transform based low bit-depth representation ME approaches are avoided. Experimental results show that the proposed approach also outperforms such low bit-depth representation based motion estimation methods previously presented in the literature, in terms of motion estimation accuracy.

Two-bit transform based block motion estimation using second derivatives

Abstract: Binary motion estimation algorithms reduce the computational complexity of motion estimation, but, sometimes generate an inaccurate motion vector. This paper proposes a novel two-bit representation, called twobit transform-second derivatives (2BT-SD) which improves the efficiency of image binarization and the accuracy of motion estimation by making use of the positive and negative second derivatives independently in the derivation of the second bit plane. The second derivatives are also used to detect flat or background regions, avoiding expensive motion vector search operations for macroblocks in these areas, and deriving the motion vectors by prediction from neighboring blocks. In applying the proposed 2BT-SD in the H.264/AVC standard, a further reduction of motion estimation complexity with a minor accuracy reduction is achieved by using 2BT-SD representation for secondary motion estimation while using the full resolution representation for the primary motion estimation. A hardware cost analysis shows that about 209 K gates of hardware logics and 2.7 K bytes of memory are reduced by 2BT-SD for motion estimation of 1280times720 size videos when compared with the full resolution motion estimation. Experiments show that the proposed 2BT-SD achieves better motion estimation accuracy than other binary motion estimations and provides faster processing time in flat or background regions with an acceptable bit-rate increase.

Detection of Duplicated Regions in Tampered Digital Images by Bit-Plane Analysis

Abstract: In this paper we present a new method for searching duplicated areas in a digital image. The goal is to detect if an image has been tampered by a copy-move process. Our method works within a convenient domain. The image to be analyzed is decomposed in its bit-plane representation. Then, for each bit-plane, block of bits are encoded with an ASCII code, and a sequence of strings is analyzed rather than the original bit-plane. The sequence is lexicographically sorted and similar groups of bits are extracted as candidate areas, and passed to the following plane to be processed. Output of the last planes indicates if, and where, the image is altered.

Truncated gray-coded bit-plane matching based motion estimation and its hardware architecture

Abstract: In this paper, an efficient low bit-depth representation based motion estimation approach which is particularly suitable for low-power mobile devices is proposed. Motion estimation is carried out using bit truncated gray-coded image pixels in the proposed approach. The hardware architecture of the proposed motion estimation method is also designed to show the effectiveness of the proposed approach. It is shown that the proposed approach provides improved motion estimation accuracy compared to the other bit-truncation based approaches. The proposed hardware architecture has low hardware complexity and consumes very low power compared to the 8-bits/pixel based hardware architectures thus, it can be easily integrated to the state of the art video encoders.

Medical Image Compression Based on Ordered Binary Decision Diagrams

Abstract: A new approach for lossless compression of medical images has been proposed. After preprocessing, the image is split into bit planes to which the compressed technique is applied. These bit planes can be expressed as ordered binary decision diagrams (OBDD) and coding. This approach compared well with WINZIP in terms of compression ratio.

Encoding device, encoding method, recording medium, and image processing apparatus

Abstract: An encoding device includes: a color-difference signal encoding unit for encoding a color-difference signal for each processing block in multiple color-difference signal encoding modes to generate multiple color-difference signal bit streams; a color-difference mode selecting unit for selecting a color-difference signal encoding mode from the multiple color-difference signal encoding modes; a luminance signal encoding unit for calculating luminance target code amount by subtracting the code amount of the encoded color-difference signal bit stream from fixed code amount, and encoding a luminance signal to generate a luminance signal bit stream; a color-difference reselecting unit for selecting the color-difference signal encoding mode corresponding to the color-difference signal bit stream having the code amount not greater than the fixed code amount, and small deterioration as to the color-difference signal; and a multiplexing unit for multiplexing the luminance signal bit stream, and the encoded color-difference signal bit stream to generate a bit stream.

Adjusting method for recording condition and optical disc device

Abstract: A method for evaluating reproduced signal wherein when Euclidean distance is calculated by judging the coincidence between a binary bit array and a predetermined evaluation bit array in the evaluation of the quality of reproduced signal, in a large capacity optical disc system with constraint length equal to or greater than 5, the assumption is made that the continuous 2T count included in a predetermined evaluation bit array is denoted by i and that each evaluation bit array is composed of a main bit array having a bit length of (5 + 2i) and auxiliary bit arrays added before and after the main bit array; judgment on whether binary bit arrays include the predetermined evaluation bit array, is concentrated on the coincidence judgment of the main bit arrays; and at the same time, the Euclidean distance between the reproduced signal and the target signal corresponding to the evaluation bit array is calculated with respect to each main bit array and the results of such calculations are separated and counted.

Method and apparatus for encoding and decoding image using image separation based on bit location

Abstract: Provided are method and apparatus for encoding and decoding an image by using a bit plane-based image encoding method and a block-based image encoding method respectively on bit planes based on the n-m most significant bits of an input image including n-bit pixel values and an image based on the m least significant bits of the input image.

Apparatus for adaptable/variable type modulation and demodulation in digital tx/rx system

Abstract: Disclosed is an adaptable/variable type modulation/demodulation apparatus. A physical layer transmission apparatus for adaptable/variable type modulation, the transmission apparatus including a classification unit to classify a bit stream according to a standard that is determined in advance after receiving the bit stream, an uncoded bit group unit to group the bit stream not to be LDPC-coded by a predetermined number of bits, an LDPC encoder to perform LDPC-coding of the bit stream, a coded bit group unit to group the coded bit stream by the predetermined number of bits, a quadrature amplitude modulation (QAM) unit to select a symbol coset using the coded bit groups; and a convolutional interleaver to perform convolutional interleaving of the symbol.

Audio encoding apparatus

Abstract: An audio encoding apparatus that encodes audio signals of a plurality of channels, includes an adaptive bit allocation control unit that adaptively controls a number of encoding bits assigned to the audio signal of each channel in accordance with perceptual entropy of the audio signal of each of the channels, a fixed bit allocation control unit that fixedly controls the number of encoding bits assigned to the audio signal of each of the channels in predetermined allocations, and a channel encoding unit that encodes the audio signal of each of the channels based on the number of adaptive allocation bits assigned by the adaptive bit allocation control unit and the number of fixed allocation bits assigned by the fixed bit allocation control unit.

Transmitter, encoding device, receiver, and decoding device

Abstract: A decoding device inputs: a redundant bit generated between data blocks contained in each of sets obtained by combining a plurality of data blocks obtained by dividing a signal bit string; and a code block obtained by error-correction-encoding the data blocks; so as to make the bit string in the code block to be an input. The decoding device calculates signal bit reliability information. Moreover, the decoding device repeats a process to use the calculated reliability information as an input to calculate new reliability information relating to a signal bit in the data block subjected to the error correction encoding into a code block. Furthermore, the decoding device repeats a process to calculate inter-block reliability information indicating the reliability of the signal bit which has contributed to generation of the redundant bit and input the inter-block reliability information, as reliability information relating to the signal bit, into an in-block repetition calculation unit in accordance with the redundant bit generated between the data blocks contained in the respective sets and the reliability information repeatedly calculated by the in-block repetition calculation unit.

Apparatus and method for modifying predicted values, and decoding system

Abstract: An apparatus for modifying predicted values in a predicted image for input to a decoder starts by taking the most significant information bit plane from the predicted image and submitting it to the decoder to be decoded. Subsequent information bit planes are then taken in descending order and submitted to the decoder, but first each of these information bit planes is modified at the locations of prediction errors identified in the preceding information bit plane by comparing that information bit plane with the corresponding decoded bit plane. The modifications improve the general accuracy of the decoded image, enabling the decoder to decode the bit planes with less additional coded information than would otherwise be required. The apparatus is useful in distributed video coding systems.

An Advanced Method for Watermarking Digital Signals in Bit-Plane Structure

Abstract: Inverting signal bits is a basic operation for data hiding such as digital watermarking. In the previous papers the level transformation that performs both inverting a specified bit and minimizing the resultant level change has been proposed. Because the transformation maps signal levels sparsely within the dynamic range, some variation of the transformed levels is necessary to conceal the fact that the signals are transformed. This paper proposes a method for varying the transformed levels randomly so that those bits that present the randomness can be distinguished. Then, these bits can represent a message to recover. Accordingly, a capacity of embedding additional bits increases. The performance of the proposed method is analyzed in a stochastic manner in terms of the resultant level distortion and an embedding capacity. A simulation result is also shown to demonstrate the actual performance in the application to digital images.

Bit mapping/demapping method and apparatus for communication system

Abstract: An improved bit mapping method and apparatus for a communication system is provided. A bit mapping method of the present invention includes arranging coded bits in a codeword in an order of recovery capability. A shift region including a number of coded bits is set. The coded bits are rearranged in the shift region by shifting the shift region by a number of bits equal to a number of bits that is indicated by a shift factor. The rearranged coded bits are mapped into a modulation symbol in an order of reliability from a lowest reliability bit position to a highest reliability bit position of the modulation symbol.

Partial error tolerance for bit-plane FIR filter architecture

Abstract: Whereas some applications require correct computation many others do not. A large domain where perfect functional performance is not always required is multimedia and DSP systems. Relaxing the requirement of 100% correctness for devices and interconnections may dramatically reduce costs of manufacturing, verification, and testing. The goal of this paper is to develop a method for trading computational correctness for an additional chip area involved by fault-tolerance implementation. The method is demonstrated for the BP array in the following way: only the most significant bits of the output word are made fault-tolerant. By introducing the concept of partially error-tolerant BP array, designers achieve one more degree of tradeoff freedom. Formal definitions of the proposed terms are given. A mathematical path based on transitive closure that generates an error significance map for the BP array is proposed. The design tradeoff is demonstrated through FPGA implementation. The achieved area savings are presented as a function of a number of most significant fault-tolerant bits.

Rate-distortion control in dvc with no feedback channel

Abstract: A method of determining bit rates for use in encoding video data for joint decoding, is disclosed. An approximation of the video data is generated for later use as side information during a process of joint decoding. Bit error probabilities are determined for each bit plane and for each coefficient band of the approximation. The bit rates are determined for encoding the bit planes depending on the bit error probabilities, bit planes, and coefficient bands.

Speech encoding using multiple bit rates

Abstract: A method system and program for encoding and decoding a speech signal including error correction data. The method comprises: receiving a speech signal comprising successive frames, for each of a plurality of frames of the speech signal, analysing the speech signal to determine side information and a residual signal, encoding the residual signal at a first bit rate, and generating an output bitstream based on the residual signal encoded at the first bit rate, and for at least one of the plurality of frames of the speech signal, encoding the residual signal at a second bit rate that is lower than the first bit rate; and generating error correction data based on the residual signal encoded at the second bit rate.

Embedding Ratio Estimating for Each Bit Plane of Image

Abstract: MSLB replacement steganography has attracted researchers' attentions. However, existing steganalysis methods for MLSB replacement steganography have been just designed under the assumption that the embedding ratios in all stego bit planes are equal. Therefore, when the messages are embedded into different bit planes with different lengths independently, a new, principled method is introduced to estimate the embedding ratio in each stego bit plane based on a sample pair model. The new method estimates the embedding ratio in each bit plane in sequence according to the priority of each bit plane's significance. A series of experiments show that the presented steganalysis method has significantly smaller bias than applying SPA method, a typical steganalysis for LSB steganography, to estimate the embedding ratio in each bit plane directly.

Method and apparatus for encoding/decoding speech signal

Abstract: An apparatus and method for encoding/decoding a speech signal which determines a variable bit rate based on reserved bits obtained from a target bit rate, is provided. The variable bit rate is determined based on a source feature of the speech signal and the reserved bits is obtained based on the target bit rate. The apparatus for encoding the speech signal may include a linear predictive (LP) analysis unit/quantization unit to determine an immittance spectral frequencies (ISF) index, a closed loop pitch search unit, a fixed codebook search unit, a gain vector quantization (VQ) unit to determine a gain vector quantization (VQ) index, and a bit rate control unit to control at least two indexes of the ISF index, the pitch index, the code index, and the gain VQ index to be encoded to be variable bit rates based on a source feature of a speech signal and the reserved bits.

Distributed hyper spectrum image compression method based on 3D wavelet transformation

Abstract: The invention provides a distributed hyper spectrum image compression method based on 3D wavelet transformation. The method comprises the following steps of: 1, dividing a hyper spectrum image into a plurality of coding units; 2, performing the 3D wavelet transformation on each coding unit of the hyper spectrum image; 3, grouping images after transformation, wherein one group is used as a reference group, and another group is used as a current group; 4, coding the reference group by a 3D SPIHT method to obtain a compression code stream of the reference group, and sending the compression code stream to a decoding end; 5, resolving the current group by an SW-SPIHT algorithm to obtain three groups of corresponding bit plane code streams which are an importance factor bit plane, an importance factor symbol bit plane and a thinning bit plane respectively; and 6, coding the importance factor symbol bit plane and the thinning bit plane of the current group by a low-density parity check code to obtain a corresponding check bit stream, transmitting the code stream of the importance factor bit plane of the current group to the decoding end, and completing the compression of the hyper spectrum image. The method has the advantages of low coding complexity and good compression property, and can be used for compressing the hyper spectrum image.

Serial Communications Device with Dynamic Allocation of Acceptance Masks Using Serial Implementation

Abstract: A CAN module or a microcontroller comprises a CAN module which receives a serial bit stream. The CAN module comprises a filter register with a bit select input and a single bit output, a bit select unit for selecting a bit of the filter register in accordance with the serial bit stream, a comparator coupled with the single bit output and with the serial bit stream for generating a comparison signal, and a register receiving the comparison signal for accumulating a plurality of comparison results and for generating an acceptance signal.

Method for aligning a serial bit stream with a parallel output

Abstract: The invention relates to a method and circuit for aligning a serial bit stream with a parallel output. The method comprises latching Q bits from the serial bit stream into a register, locating a position P of a first bit of a start of frame delimiter (SFD) in the register and discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output. The circuit comprises a latch, a fault tolerant analysis logic (FTAL) for locating a position P of a first bit of a start of frame delimiter (SFD) in the register and a shift register for discarding P-1 bits from the serial bit stream, before the position of the first bit of the SFD, thereby aligning the serial bit stream with the parallel output.

Entropy encoding and decoding method and apparatus using least significant bit

Abstract: Provided are entropy encoding and decoding methods. The entropy encoding method includes receiving residual coefficients obtained by frequency converting a residual image, determining a first bit string about residual coefficients having nonzero levels from among the received residual coefficients, determining at least one lower bit, including a least significant bit of the first bit string, from the first bit string, and determining a second bit string obtained by bit-shifting the first bit string to the right by the number of lower bits.

Identification of potentially erroneous and/or erased data

Abstract: Systems for identifying potentially erroneous and/or erased data are provided. Systems have a bit detector, an accumulator, and a data reconstruction processor. The bit detector assigns values to bits read in a data signal. The bit detector illustratively assigns multiple values to each of the bits. The accumulator accumulates a count of the multiple values assigned by the bit detector for each of the bits. The accumulator associates each bit with a particular value based at least in part on its accumulated count. The data reconstruction processor determines for each of the bits a confidence level of the particular value associated to it. The data reconstruction process sets flags for a portion of the bits. The flags identify the portion of the bits as possible erased or erroneous data. The flags are set based at least in part on the confidence levels of the portion of the bits.

Method and system for writing a reference frame into a reference frame memory

Abstract: In a method and system for writing a reference frame having multiple pixels into a reference frame memory, the pixels of the reference frame are sampled to obtain a plurality of representative pixels. A multi-bit pixel value of each of the representative pixels is divided into a number (N) of bit sections, each corresponding to one of a number (N) of different bit significance levels, based on a bit depth, where N is associated with the bit depth. The bit sections of the pixel values of the representative pixels having the same bit significance level are arranged together to form a number (N) of bit depth planes each including the bit sections that have a corresponding one of the bit significance levels. The bit depth planes are stored in the reference frame memory.

Radio communication device and error correction/encoding method

Abstract: Provided is a radio communication device which can obtain an error ratio characteristic equivalent to the one obtained by using a tail bit, without using a tail bit in the error correction and encoding. The device includes: a blocking unit (106) which adds a bit indicating an error detection result in a CRC unit (105) to control data (a bit string) so as to constitute an encoded block and outputs the encoded block to an encoding unit (107); and the encoding unit (107) which corrects and encodes the encoded block. The blocking unit (106) forms an encoded block by a bit string of control data and a probability deviation existence bit added to the tail of the bit string.

Optimization of Bit Plane Combination for Efficient Digital Image Watermarking

Abstract: In view of the frequent multimedia data transfer authentication and protection of images has gained importance in todays world. In this paper we propose a new watermarking technique, based on bit plane, which enhances robustness and capacity of the watermark, as well as maintains transparency of the watermark and fidelity of the image. In the proposed technique, higher strength bit plane of digital signature watermark is embedded in to a significant bit plane of the original image. The combination of bit planes (image and watermark) selection is an important issue. Therefore, a mechanism is developed for appropriate bit plane selection. Ten different attacks are selected to test different alternatives. These attacks are given different weightings as appropriate to user requirement. A weighted correlation coefficient for retrieved watermark is estimated for each of the alternatives. Based on these estimated values optimal bit plane combination is identified for a given user requirement. The proposed method is found to be useful for authentication and to prove legal ownership. We observed better results by our proposed method in comparison with the previously reported work on pseudorandom watermark embedded in least significant bit (LSB) plane.