Showing papers on "Blackfin published in 2006"
17 Jun 2006
TL;DR: This paper describes the use of the embedded DSP platform based on the Analog Devices Blackfin digital signal processor in the Microprocessor-based Design Laboratory and discusses how this platform can be used in a range of classes.
Abstract: At Northeastern University we are building a number of courses upon a common embedded systems platform. The goal is to reduce the learning curve associated with new architectures and programming environments. The platform selected is based on the Analog Devices Blackfin digital signal processor.In this paper we discuss our recent experience developing anew undergraduate embedded systems lab. Students learn to utilize the embedded DSP platform to address a number of different applications, including controller design, RS-232 communication, encryption, and image processing. This platform provides a rich design exploration sandbox replete with programming and simulation tools. We describe our use of this platform in our Microprocessor-based Design Laboratory and discuss how this platform can be used in a range of classes.
11 citations
14 Jun 2006
TL;DR: A new algorithm is introduced for the control of ACIM and the power inverter with embedded systems fault prediction and diagnosis and embedding a systems condition analysis algorithm in to the motor control algorithm results in an integrated approach.
Abstract: Fault diagnostics of AC induction machines (ACIM) have been widely researched however, an integrated algorithm for motor control with automated fault detection, prevention and condition monitoring is still missing. Condition monitoring can reduce the downtime of the processes and increase the maximum interval between failures, thus minimizing the number and cost of unscheduled maintenances, which is highly beneficial. In addition, embedding a systems condition analysis algorithm in to the motor control algorithm results in to an integrated approach; this can reduce the cost of the system and enhance its integrity. Thus, a new algorithm is introduced for the control of ACIM and the power inverter with embedded systems fault prediction and diagnosis. The embedded control and diagnostics algorithm is implemented using the analog devices Blackfin/spl trade/ ADSP-BF561 dual core digital signal processor (DSP). Core 1 is dedicated to implement the control algorithm while core 2 mainly implements the fault prediction and diagnostics algorithm. The diagnostics algorithm can shutdown the drive system on an imminent catastrophic fault. The algorithm employs various techniques to detect and predict different faults of the AC drive system. In this paper, the inverter fault prediction and diagnosis are covered. The DSP communicates the systems electrical and mechanical parameters to a Windows XP/spl trade/ PC through the USB connection, which is mainly used to monitors and displays the electrical parameters of the inverter and the motor it also allows update of the DSP controller for speed/torque adjustments.
7 citations
28 Nov 2006
TL;DR: The improvement in performance has been evaluated for each optimization step and the results of the optimization demonstrate the potential of the low- power Micro-Signal Architecture of Blackfin processor as a good choice for next generation embedded multimedia applications.
Abstract: Real-time video images communication needs efficient implementation and optimization about the video compression algorithms on power-efficient platforms. To meet such needs several compression methodologies and techniques have been proposed and standardized. This paper presents the implementation details of H.264/AVC (the latest standard for video compression) encoder on ADSP-BF537 processor based Analog Devices BF537-STAMP board, and gives several optimization techniques which have been concurrently employed in this work to improve the performance of the encoder. In this paper, the improvement in performance has been evaluated for each optimization step and the results of the optimization demonstrate the potential of the low- power Micro-Signal Architecture of Blackfin processor as a good choice for next generation embedded multimedia applications.
4 citations
01 Jan 2006
TL;DR: Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices Engineer-to-Engineer Notes.
Abstract: Copyright 2006, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices Engineer-to-Engineer Notes. Introduction
3 citations
20 Sep 2006
TL;DR: This paper presents an extension of the OpenMP shared directive for performance optimization on BlackFin 561 (ADSPBF561) dual core processors and shows how this extension could improve the speedup by up to 107% and reduce the energy consumption byUp to 108% in measured benchmarks with respect to no use of the extension.
Abstract: Many researchers and vendors are exploiting the increasing number of transistors to build chip multiprocessors (CMPs) by partitioning a chip into multiple simple ILP cores. As in traditional multiprocessors, CMPs extract thread-level parallelism (TLP) from programs by running multiple independent program segments, i.e., threads, in parallel. Currently CMPs are used widely in high performance servers, and even in embedded systems. In this paper, we present an extension of the OpenMP shared directive for performance optimization on BlackFin 561 (ADSPBF561) dual core processors. In order to support memory consistency between multiple cores, many architectures have been proposed. On the dual core processor, like ADSP-BF561, each core has its own private L1 cache, and a shared L2 cache. In order to execute multithreaded parallel programs, we need to consider carefully where to allocate shared variables on targeted memory architecture. We could improve the speedup by up to 107% and reduce the energy consumption by up to 108% in our measured benchmarks with respect to no use of our extension.
3 citations
Journal Article•
1 citations
01 Jan 2006
TL;DR: A novel approach for resizing of images in the spatial domain is presented, seen from a Euclidean space perspective and expressions for image resizing are derived.
Abstract: A novel approach for resizing of images in the spatial domain is presented. Image transformations are seen from a Euclidean space perspective and expressions for image resizing are derived. The proposed method can be used for resizing by any arbitrary rational ratio L/M. The algorithm has been tested for resizing between standard formats like NTSC, QVGA, QCIF and CIF and the performance is compared with other algorithms in terms of PSNR and computational efficiency. Real time implementation on analog devices Blackfin-BF533 DSP processor shows promise.
01 Jan 2006
TL;DR: Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices’ Engineer-to-Engineer Notes.
Abstract: Copyright 2004 2006, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices’Engineer-to-Engineer Notes. Introduction
01 Jan 2006
TL;DR: This report covers a master thesis in signal processing that deals with solving a problem in a special type of audio encoder used in the Swedish speech newspaper system.
Abstract: This report covers a master thesis in signal processing. It deals with solving a problem in a special type of audio encoder used in the Swedish speech newspaper system. However, design methods an ...
01 Jan 2006
TL;DR: This paper has designed and implemented a Blackfin DSP-based, high performance, low cost, low power consumption, real time network video encoder for MPEG-4, H.263 network video surveillance system.
Abstract: Video encoder is an important part of video network surveillance system, and its design goals include combining real time coding, high performance, low cost and flexible control with small size. To meet all these requirements, DSPs with video ports provide an ideal solution. In this paper, we've designed and implemented a Blackfin DSP-based, high performance, low cost, low power consumption, real time network video encoder. The hardware system, software flow, algorithm optimization, Ethernet transmission and performance test are discussed in detail. This network video encoder has been successfully used in our MPEG-4, H.263 network video surveillance system
01 Jan 2006
TL;DR: This thesis examines general design issues for constructing a high performance port of L4 without virtual memory but with memory protection and provides a concrete implementation by porting L4 to the Blackfin processor.
Abstract: The L4 microkernel is used as the basis for several operating systems but was built on the assumption of virtual memory. This thesis examines general design issues for constructing a high performance port of L4 without virtual memory but with memory protection. It also aims to provide a concrete implementation by porting L4 to the Blackfin processor. The results of our research were found to be general, and not just Blackfin-specific. Therefore, we enable L4 to support an additional category of processors – those without virtual memory. Our L4 implementation on Blackfin verifies the validity of the design. While it outperforms ucLinux, at least on context switching time, there is still much work to be done before it is deployable.