Showing papers on "Boolean circuit published in 1974"

Combinational complexity of some monotone functions

Abstract: An important open question in the field of computational complexity in the development of nontrivial lower bounds on the number of logical operations required to compute switching functions. Although counting arguments can be used to show that most Boolean functions of n inputs and 0(n) or fewer outputs have complexity growing exponentially in n, no one has yet exhibited a particular such function whose unlimited fan-out combinational complexity is known to grow faster than linearly in n when a functionally complete set of primitive operations is allowed. In this paper, we consider the class of monotone increasing Boolean functions. These correspond to the functions which can be computed using only two-input OR and AND operations, an incomplete set of primitives. We develop techniques for proving functions of n inputs and 0(n) outputs have nonlinear combinational complexity if only OR and AND operations are allowed. We do this by demonstrating that binary sorting requires 0(n log n) operations, and by exhibiting a set of n Boolean sums over n variables which requires 0(n3/2) operations.

The power of negative thinking in multiplying Boolean matrices

Abstract: We are interested in combinational circuits synthesized from and-gates and or-gates. We first show that n3 distinct and-gate inputs are needed to form the product of two Boolean matrices, and hence O(n3) two-input and-gates are needed to compute the transitive closure of a Boolean matrix. While this result has the flavor of Kerr's (achievable)lower bound [Kerr 1970] of n3+-gates for computing the min/+ product of integer-valued matrices using only min-gates and +-gates, the problem turns out on closer inspection to be considerably more subtle, and in fact we have been able to come only to within a factor of two of the best known upper bound of n3and-gates.Secondly we use this result to study the effect on combinational circuts of not using not-gates inverters).

Unateness Properties of and-Exclusive-or Logic Circuits

Abstract: Reordering the terms of a Reed-Muller or ring sum expansion of a switching function expressed in terms of the Boolean ring operations AND and EXCLUSIVE OR in a more natural way exploits the similarities between these expressions and unate functions and displays mathematical structure which apparently has not been noted before. McNaughton's n orderings on the n cube appear in a new setting and lead quickly to simple but geometrically satisfying theorems dealing with a matrix of coefficients of all 2n ring sum expressions for various polarities of inputs. The structure of these matrices for minterms, implicants, and functions are shown to have simple and attractive forms. An algorithm is presented which allows simple determination of a ring sum realization using logic array notation, and which can also be used to find minimum cost polarities. A second algorithm allows nonexhaustive and near-optimal handling of functions with DON'T CARE conditions.

A Boolean Model for a Class of Discrete Event Systems

Abstract: A Boolean matrix equation model is obtained for a class of discrete event systems in which the state change associated with each event occurrence is deterministic, and in which all entities are permanent. The Boolean matrix equations are quite compact and can be efficiently programmed on a digital computer. A conveyor system is used as an example. The model can be investigated for determinacy, zero states, and cycles. Algorithms are presented that determine whether transient events interact, and whether transient cycles exist. The zero states of a model are shown to be solutions of a simple Boolean matrix equation.

Lamp: Automatic test generation for asynchronous digital circuits

Abstract: An automatic test generation system has been developed to detect faults in combinational and sequential circuits. The circuit model treats logic circuits as interconnections of unit- and zero-time-delay gates. A series of time-dependent Boolean equations are derived from the logic network (starting from the network inputs) in terms of sequences of signals (input vectors) on the circuit input leads. These equations account for the effect of specific circuit faults. Many tests, each consisting of a sequence of input signals (input vectors), are needed to detect all single faults in a circuit. Tests are generated from the time-dependent equations using two different strategies: (i) a maximum-cover approach to detect a large number of faults quickly by generating tests for the faults on the circuit-input leads. The fault-detection level achieved by the maximum-cover tests is then evaluated using fault simulation; (ii) tests for individual faults not detected by the maximum-cover approach. ATG has been implemented on the IBM 360, Model 67, and IBM 370, Model 168, computers.

Adaptive boolean logic element

Abstract: A digital logic circuit, hereinafter referred to as an element, of which an interconnected plurality together with their connections to a control unit comprise a learning machine which synthesizes a boolean function of n variables as the result of a training procedure. Each element may operate as a two-input, one-input combinational circuit of one of four logical types, where the type is determined by the current internal state of the element. All four types are such that a (ZERO,ZERO) input pair gives rise to a ZERO output, and a (ONE,ONE) input pair gives rise to a ONE output, while the particular operation realized is determined by two function value units which compute suitable outputs under the (ONE,ZERO) and (ZERO,ONE) input pairs to the element. Three different species of element are described differing in their computation of heuristic responsibility. The "global search" species is useful when the function to be synthesized is not constant; there is a convergence theorem related to this species. The "latest error" species is also useful for applications where the function to be synthesized may be a constant; but this type does not obey a known convergence theorem. The "hill climbing" species is useful principally to improve an existing approximate synthesis. Means are provided for setting and reading out the functions realized by the elements in a tree-like network in order to facilitate storage and transmission of synthesized functions.

CMOS Boolean logic mechanization

Abstract: Unique, relatively simplified circuits employing complementary metal oxide semiconductor transistors and suitable diode means to mechanize the Boolean functions A.sup.. B and A+B and combinations thereof. In a preferred embodiment, the transistors and diodes may be fabricated by silicon-on-sapphire integrated circuit techniques. The circuits obviate the need for a conventional NOR or NAND gate which is common to logic gating arrangements of the prior art. Hence, the number of components and the corresponding cost of the circuit are reduced while the operating speed thereof is increased.

Serial programmable combinational switching function generator

Abstract: A device for performing logic operations in which a Boolean equation to be solved is serially processed in a manner which results in a large reduction in the number of building blocks required while still allowing the solution of long logic equations.

Equational Logic

Abstract: A combinational circuit realizing the switching function f(x) may be regarded as a solution verifier for the Boolean equation f(x) = 1. (*) The output of the circuit is 1, that is, if and only if the input-vector x is a solution for (*). We use the term "equational logic" to denote an approach to circuit synthesis based on (*) rather than on the function f(x). The central problem of equational logic is to find a system of equations gi(x) = hi(x) (i = 1,2,...,k), of the simplest possible form, that has the same solutions as (*). Given such a k-equation system, f(x) may be realized as the output of a k-wide digital comparator whose inputs are the 2k g's and h's constituting the system. The problem of finding a simple system of equations equivalent to a given equation was investigated more than a century ago by Willian Stanley Jevons, who called it "the inverse problem of logic." It was thought by Jevons and other 19th century logicians that the inverse problem is "always tentative," i.e., that it does not admit of algorithmic solution. It is shown in this paper, however, that the inverse problem may be solved as a covering problem by use of the "table of consequences" of Poretsky. As presently formulated, this approach is limited in practical utility by the large size of the tables involved. It appears that a practical solution technique requires a reformulation of the inverse problem.

A Method of Digital Computation for SCR Circuits

Abstract: It is shown in this paper that it is possible to derive generalized equations for computation of electrical circuits containing SCR elements. Any classical method of circuit analysis can be used applying the nonlinear mathematical model given for the SCR. In order to get this model, a binary logic state variable is doped to the equation which is obtained by a Boolean function. The derivation of this mathematical model and the application of the method to an impulse-commutated inverter with an RL load are presented.

A Computer Algorithm for the Synthesis of Memoryless Logic Circuits

Abstract: A method has been investigated for the synthesis of memoryless logical networks using a restricted repertoire of functional modules. The method is based on the reduced general solution to a generalized system of Boolean equations (BE) as applied to the decomposition of Boolean functions. The aim of the synthesis is to obtain the most constrained circuit having at most two levels of gating. The constraints take the form of single input variables or constant logic levels applied to the inputs of the first level gate. This is achieved by assembling a set of constraint equations which are then a part of the generalized system of BE. The method is then tested on some synthesis examples of single and multiple output functions in terms of the NAND and (WOS) modules.

Evaluating Boolean function with random variables

Abstract: The paper considers the determination of the value of a boolean function by examining its variable. The function's value is deterministically determined by the variables which arc binary and random. A sequential testing procedure of the variables is presented. It is shown that this procedure minimizes the expected number of necessary tests for some classes of functions and probably do so for others. The presence of such problem is described in file searching, reliability systems, switching circuits and graph connectivity.

On the Solution of Boolean and Pseudo-Boolean Relations

Abstract: This correspondence deals with collections of n binary relations between Boolean and/or pseudo-Boolean functions which are combined by an n-ary relation. A new algorithm is described for solving these relations.

Extension of Boolean differentiation to define a test for a specific logic fault in a combinational logic network

Abstract: The letter demonstrates an extension of Boolean difference to obtain a test for a specific fault. The extension is compared with Roth's D calculus, and it is shown that the two concepts are complementary. A procedure for determining the total fault-detection capability of each test is indicated.

A new heuristic test generation algorithm for sequential circuits

Abstract: This paper describes a new heuristic algorithm for the computation of tests to detect failures in sequential logic circuits. In the algorithm, the values of logic blocks in a logic circuit are expressed in boolean vectors with six elements and main process of the algorithm is the operations among these values. Presented in this paper are basic principles for the algorithm, their application procedure with an example and our experiences through the implemented system.

T01A-programming languages: T01A5-Computer-aided boolean algebra

Abstract: A system allowing fast boolean manipulation on a CYBER 74 has been written.1 This set of Compass and Fortran routines allows definition and processing of boolean monomials and polynomials of up to 48 variables. Elementary boolean operations (AND, OR, EXCLUSIVE-OR,...) as well as complex special-purpose manipulations (CONSENSUS, BOOLEAN DIFFERENCE .... ) are defined. Evaluations of polynomials is also possible. A comprehensive set of input-output functions allows a user to define polynomials either explicitely in terms of monomials written in algebraic form or, more compactly, by means of a list of decimal numbers each o f which is equivalent to one product. The system is presently under test for complex algorithms like the covering problem2 (combinational circuit minimization) and test vector generation.3 It will be described and results from these preliminary experiments will be given.

On Boolean functions having maximal number of subfunction classes

Abstract: Advances in LSI technology have led to problems concerning the selection of output functions for optimum complex logic modules. A natural criterion for the evaluation of possible designs is the structure of the set of all subfunctions of the function realized by a module. Thus studying properties of the sub-function sets of Boolean functions is an approach to solving the above problems. In the paper some general results on Boolean functions having the largest sets of subfunction classes are presented and methods for constructing such functions are discussed.

Application of the Boolean-difference technique to sequential logic

Abstract: The letter describes the application of the Boolean-difference technique to sequential circuits by demonstrating that the sequential property of memory can be attributed to the concatenation of two sensitive paths. This leads to a behavioural description of a JK bistable, forming a basis for test generation for sequential networks.