Showing papers on "Bus network published in 1976"

Reconfigurable data bus

Abstract: A digital data communication system having a plurality of digital nodal communication devices interconnected by a digital data bus in a fixed physical manner in which the data bus structure may be electrically reconfigured without physical modification of the digital data bus. The ability to reconfigure the digital data bus is accomplished by the insertion of a digital reconfigurable data bus module into the position on the digital data bus previously held by one of the digital nodal communication devices and the connection of the replaced digital nodal communication device to the digital reconfigurable data bus module. The digital reconfigurable data bus module contains a transceiver mechanism capable of receiving and transmitting digital information to and from the digital data bus, an adapter mechanism for communicating with the replaced digital nodal communication device and a switching mechanism capable of the multiple switching of data from the adapter section which is connected to the replaced digital nodal communication device to the transceiver section which is connected to the digital data bus. The digital reconfigurable data bus module allows a fixed configuration of nodal devices and connecting devices to provide the function of tree structured buses, ring structured buses, dedicated channels or combinations of any of them. The module facilitates the receipt, switching and retransmission of data on any selected bus pattern.

Microprocessor architecture with integrated interrupts and cycle steals prioritized channel

Abstract: A computing system architecture includes a central processing unit having a channel, arithmetic and logic unit, a plurality of working registers, and control logic; a plurality of local storage registers; a main storage; an executable control store; one or more input/output devices; and a multiplexed cycle steal and interrupt request common poll bus. The storage and input/output devices communicate with and are controlled by the central processing unit over a looped, or unidirectional bus and control channel including a bus in, a bus out, an address and control bus, and a plurality of control lines. Bus out is operated to address the executable control store and main storage, and to provide data to the input/output devices and the local storage registers. Bus in is shared by the input/output devices and all storage devices and registers for transferring data and control information to the central processing unit. Bus in is also used by main storage to receive data from the input/output devices and from the local storage registers. The address and control bus addresses the input/output devices and the local storage registers, thus enabling overlapping of device or local storage data transfers with the accessing of executable control storage and main storage, and with instruction execution. The arithmetic and logic unit is time shared for data and input/output processing, register/register and storage/register transfers, shift operations, byte manipulations, and address modification. Both cycle steal and interrupt requests are received by the central processor on the common poll bus.

Priority network for devices coupled by a common bus

Abstract: A priority network utilizing a common bus coupled to a plurality of priority seeking peripheral devices wherein a processor or any number of processors is connected to the common bus. Each successive peripheral device is connected to the common bus in increasing priority order, such that each device will have a unique priority defined. Each peripheral device is provided with an associated peripheral control unit. Each of the peripheral control units is connected in serial fashion on an enabling line with the output of the higher priority control unit providing an enabling input to the next lowest priority peripheral control unit, such that the highest priority device requesting bus access prevents all lower priority devices from gaining access to the common bus until the higher priority device has completed its data transfer.

Asynchronous bidirectional interface with priority bus monitoring among contending controllers and echo from a terminator

Abstract: An interface which connects input/output (I/O) controllers to a data channel in a data processing system. A bidirectional priority bus is provided interconnecting the channel with the controllers. Each controller is assigned a priority level. When a controller requires service, it signals the channel over a common request line and the channel responds with a channel select signal. Each requesting controller gates a binary number corresponding to its priority level onto the common priority bus. Contending controllers resolve priority among themselves by monitoring the priority bus. If a controller detects a higher priority level than its own level on the bus it removes its priority number from the bus. The highest priority controller then activates an acknowledge signal and places its device address on a bidirectional data bus in response to a ready signal from the channel.

Interactive graphics system for transit route optimization

Abstract: A person-computer interactive graphics system for optimizing the routing structure on an urban transit network is presented. The system allows a user to design bus, streetcar, and subway routes on a display scope and to specify route frequencies and types of vehicles. The computer predicts the effects of the routing structure by assigning potential transit trips to the network and it displays the route loadings along with statistics on travel times, rolling stock use, and operating costs. After evaluation, the user can partially or totally modify his or her designs and thereby move toward routing schemes that come closest to planning objectives. The system is based on a multipath transit assignment model that is a further development of R. B. Dial's stochastic assignment algorithm. The model is implemented on a CDC 7326 series computer with a display scope, and it has been tested by being applied to the Lausanne, Switzerland, public transit system. A second implementation of the model has been realized on a small computer environment and is being used productively for optimizing the 24-route tramway and bus network of Basel, Switzerland. The methodology and some results of these applications are described.

Network testing method and apparatus

Abstract: The present invention provides method and apparatus for testing a network, such as a printed circuit board, to check whether it conforms to its design as to having a plurality of network nodes and a predetermined node-connection pattern defining a division of the network nodes into a plurality of groups. In a conforming network, each network node is connected in common to all other network nodes in its group, and is isolated from the network nodes in each other group. In accordance with the invention, one of the network nodes is selected to serve initially as a present FROM node. There is thereafter selected repeatedly, from the network nodes that have not previously served as a present FROM node, a network node to serve temporarily as a present FROM node. Each time a network node is selected to serve as a present FROM node, there is selected a network node, from the group containing the present FROM node, to serve temporarily as a present TO node such that, as to each group, network nodes thereof are sequentially selected to serve as TO nodes in the same order that they are sequentially selected to serve as FROM nodes. Each time two different nodes are selected as present FROM and TO nodes, continuity therebetween is verified.

Demand Model for Bus Network Design

Abstract: A demand model based on the concepts of transit accessibility and route directness was developed. Transit accessibility was expressed in terms of transit service coverage and transit service frequency. Route directness, on the other hand, was measured by a meandering penalty. The two measures were then combined into a single index, on which the estimation of transit demand was based. The development of the current model ensures a sensitive relation between the design of network configuration and the estimation of transit demand, therefore providing transit planners a better tool in bus network design.

Self-memorizing data bus system for random access data transfer

Abstract: A data bus system is disclosed for transferring data from one process area to another without synchronizing bus input and output functions. Data is driven onto the bus when available. When data is not being actively driven onto the bus, the bus will latch to its last driven state. The data may then be randomly accessed.

Bus switching unit for electronic computer

Abstract: PURPOSE: To secure an easy common use of an input/output unit given from plural processors by means of one unit of bus switching unit, by providing a priority circuit to the bus switching unit and by holding directly the input/output unit in common COPYRIGHT: (C)1978,JPO&Japio