Showing papers on "Carry flag published in 1994"

Logic structure and circuit for fast carry

Abstract: Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things, for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal. For each bit, a carry propagate signal is generated by a lookup table programmable function generator and is used by dedicated hardware to generate the carry signal.

Flag renaming and flag masks within register alias table

Abstract: A mechanism and method for renaming flags within a register alias table ("RAT") to increase processor parallelism and also providing and using flag masks associated with individual instructions. In order to reduce the amount of data dependencies between instructions that are concurrently processed, the flags used by these instructions are renamed. In general, a RAT unit provides register renaming to provide a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs, for instance) to eliminate false data dependencies between instructions that reduce overall superscalar processing performance for the microprocessor. The renamed flag registers contain several flag bits and various flag bits may be updated or read by different instructions. Also, static and dynamic flag masks are associated with particular instructions and indicate which flags are capable of being updated by a particular instruction and also indicate which flags are actually updated by the instruction. Static flag masks are used in flag renaming and dynamic flag masks are used at retirement. The invention also discovers cases in which a flag register is required that is a superset of the previously renamed flag register portion.

Method for compression of binary data

Abstract: The disclosed method for compression of a series of data bytes, based on LZSS-based compression methods, provides faster decompression of the stored data. The method involves the creation of a flag bit buffer in a random access memory device for temporary storage of flag bits generated during normal LZSS-based compression. The flag bit buffer stores the flag bits separately from their corresponding pointers and uncompressed data bytes until all input data has been read. Then, the flag bits are appended to the compressed output stream of data. Decompression can be performed much faster because bit manipulation is only required when reading the flag bits and not when reading uncompressed data bytes and pointers. Uncompressed data is read using byte length instructions and pointers are read using word instructions, thus reducing the time required for decompression.

Compressed digital multi-channel video communications system having one or more auxiliary channels to accomodate high bit rates

Abstract: A compressed digital multi-channel video communications system having at least one auxiliary channel. The other channels are assigned to respective program sources. These channels are prioritized. The auxiliary channel works with the assigned channel which has the highest priority and which also requires additional bit capacity; the two channels carry bit streams whose combined rate exceeds the highest bit rate that can be carried by a regularly assigned channel. As the needs of the assigned channels continuously change, the auxiliary channel works with different channels.

Structure and method of using an arithmetic and logic unit for carry propagation stage of a multiplier

Abstract: A multiplier circuit for use in a system which includes an arithmetic and logic unit (ALU). The multiplier circuit includes a carry save stage which receives a first data value and a second data value, and in response, creates a carry signal and a sum signal. The carry and sum signals are provided to input leads of the ALU. The ALU is used to add the carry and sum signals to create a third data value which is equal to the product of the first and second data values. In one embodiment, the input leads to the ALU are multiplexed. Thus, one input lead of the ALU receives either the carry signal or a signal from a first input node and the second input lead of the ALU receives either the sum signal or a signal from a second input node.

Electronic computing unit (arithmetic unit)

Abstract: There is proposed an electronic computing unit, such as an arithmetic logic unit (ALU), a processor, a controller or the like, for the arithmetic logic combination of digital operands (A, B), which are coded by means of code bits and are supplied via at least one data bus (11, 12), to form data words (S) which are likewise coded by means of code bits, the arithmetic logic combination of the bits of the operands taking place in stages and at least one carry bit (U) being formed in each stage. A code forming unit generates from the coded operands the code bits of the result word, taking into account the required operation. An additional carry forming device (22, 23) is assigned to the individual stages. A testing device (32) for checking the carry bits which have been formed twice for identity is further provided. Finally, there is additionally provided for each operand (A, B) a code testing device (33, 34), which is connected via connecting lines (13-16) to the individual lines of the at least one data bus (11, 12), the computing unit (10) and the carry forming device (22, 23) being connected to the connecting lines (13-16) between the code testing device (33, 34) and the data bus (11, 12). In this way, it is possible to identify not only erroneous operand bits and carry bit but also interruption faults of operand bit lines.

Look ahead carry type adder

Abstract: PURPOSE:To improve processing speed by speeding up the fixing of a code flag. CONSTITUTION:A look ahead carry type 4-bit adder 20, a look ahead carry type 3-bit adder 70 and look ahead carry type 4-bit adders 40 and 50 are cascade-connected to the input/output terminal of carry, the carry output terminal of the most significant side look ahead carry type 4-bit adder 50 is connected to the carry input terminal of a 1-bit adder 74, the sum output terminal and carry output terminal of the 1-bit adder 74 are respectively connected to the input terminal of a code flag SF and the input terminal of a carry flag CF, the carry is supplied to the 1-bit adder 74 through the carry look-ahead parts of the plural look ahead carry type adders, the code bit can be calculated from this carry, most significant augend bit and most significant addend bit and therefore, the fixing of the code flag SF can be speeded up.

Parallel carry generation network, parallel adder network, carry generation module, multibit adder network and modular carry propagation unit

Abstract: PURPOSE: To provide an N-bit binary adder with highly parallel structure improving a speed. CONSTITUTION: The adder 500 consists of a plurality of parallel module two adders forming the sum of an arithmetic number and a carry bit. A carry input is generated by a conditional propagating generator 400 and an unconditional carry generator 300 generating a carry bit at a log2 2N arithmetic level.

Multiplication circuit over integer

Abstract: PURPOSE:To provide the efficient circuit considering carry by using a multiplier with the small number of digits in the case of separately calculating an input value with the large number of digits in the multiplication circuit CONSTITUTION:This circuit is provided with multipliers B10-B13 of mXm bits which input an integer A from the high-order digit while dividing it into (n) clocks for every (m) bits and multiply the prescribed (m) bits of an integer B to the respective (m) bits of the integer A, three-input (m) bit full adders +10-+13 with carries for adding the low-order (m) bits of outputs from the high-order digit multiplier, the high-order (m) bits of outputs from the same digit multiplier, the output of the (m) bit full adder with carry at the following digit in the case of the last clock, and the carry bit of the (m) bit full adder with carry at wo digits behind in the case of the last clock, (m+1) bit registers R10-R13 connected between two of three-input (m) bit full adders with carries Then, the content of the (m+1) bit register in the final step after each clock is defined as the output of a multiplied result AB from the high-order digit

Means for calculating parity bits associated with a sum of two numbers

Abstract: In an adder that finds the sum of two binary numbers A and B, it is now conventional to associate one or more parity bits (PA, PB, PS) with each of the two numbers A and B and the result S. Each number A and B and the result S is divided into K groups each of m bits, and one parity bit is associated with each group. In accordance with the invention, the parity PS associated with the result S is obtained at the same time as the result. The input carry bit c i n intervening in the addition is available before the beginning of operations. Consequently, it is used in a first stage 10' upstream of the device, which calculates intermediate variables p i ,j and g i ,j. The other input carry bits c i ,1 corresponding to the other groups are determined only later by a carry look ahead circuit, and consequently they are used only in a second stage 50' downstream of the device. The use of c i n in the first stage 10' makes it possible to perform the calculation of the parity bits and look ahead for the carry bits with a single circuit present in a third stage 60, which is intermediate between the first stage 10' and the second stage 50'.

Ein rechnergestütztes Verfahren zum Konstruieren eines Addierers mit vorgreifender Übertragsbildung A computerized method for constructing an adder with carry-generating anticipatory

Abstract: A computer program for designing a carry-lookahead adders which add two binary numbers of various bit-widths, and an input carry bit.

Ein rechnergestütztes Verfahren zum Konstruieren eines Addierers mit vorgreifender Übertragsbildung

Abstract: A computer program for designing a carry-lookahead adders which add two binary numbers of various bit-widths, and an input carry bit.

Method and circuit for counting down the value of a debit-card

Abstract: In a method and a circuit for carrying out the method of counting down the value of a debit card, the memory is used as a multi-stage counter. Each counter stage is assigned one bit of a control memory. To prevent the card value from being manipulated, it is provided that before writing a carry and erasing the lower-order counter stage, the carry bit and the check bit are read with various evaluation thresholds. Such a circuit can be realised with a high level of immunity to manipulations by uncomplicated circuitry.

A computerized method for constructing an adder with carry-generating anticipatory

Abstract: A computer program for designing a carry-lookahead adders which add two binary numbers of various bit-widths, and an input carry bit.