Showing papers on "Carry flag published in 1999"

Instruction having bit field designating status bits protected from modification corresponding to arithmetic logic unit result

Abstract: A data processing apparatus includes plural data registers, an arithmetic logic unit and a status register. The status register stores a plurality of different types of status bits. These status bits could be a negative status bit, a carry status bit, an overflow status bit and a zero status bit. These status bits are normally set dependent upon the condition of the result generated by the current arithmetic logic unit operation. A status bit protect instruction type permits selection of status bits protected from modification corresponding to the current arithmetic logic unit result. This status bit protect instruction preferably includes individual protect bit corresponding to each status bit. If a protect bit has a first digital state, then the corresponding status bit may be modified corresponding to the current arithmetic logic unit result. If the protect bit has a second opposite digital state, then the corresponding status bit is protected from modification according to the arithmetic logic unit results.

Checksum generator with minimum overflow

Abstract: A checksum generator includes at least one adding circuit for processing a segment of a given message. Associated with the adding circuit is a register for temporarily holding the partial sum that is being calculated by the adding circuit. The register is configured to hold a partial sum that is larger than the message segments being added by the adding circuit. The partial sums can thus expand into the register, eliminating the creation of a carry bit that must be added back in during each add cycle. After the last message segment has been processed, the adding circuit preferably adds the high order portion of the register to the low order portion and adds back any carry bit generated thereby to produce a checksum value that may be loaded into the given message.

Conditional carry encoding for carry select adder

Abstract: The inventive mechanism encodes the carry in as well as the operand bits for each place in a binary addition of two streams of bits. The carry ins are encoded as Propagate (Pin), Kill (Kin), and Generate (Gin), with respect to the carry in to a block of bits. Only one of the signals would be high at any time, and the other two would be low. The Pin signal for a bit is true where the bit has a carry in that is the same as the carry in to the block of bits, i.e., the carry in to the block is propagated up to the particular bit. The Kin signal for a bit is true where a carry in to the bit is zero regardless of the carry in to the block, i.e., any carry in to the block is killed before it gets to the bit. The Gin signal for a bit is true where the bit has a carry in of one regardless of carry in to the block, i.e., the carry in to the bit is generated within the block. These signals are used in the calculation of the sum of the operand bits.

System for synchronizing use of critical sections by multiple processors using the corresponding flag bits in the communication registers and access control register

Abstract: A hardware arrangement for implementing synchronization control between multiple processors is disclosed. The hardware arrangement is provided with a plurality of communication registers which are arranged so as to store synchronization control data applied from the processors. A flag bit register generates a plurality of flag bits which are respectively assigned to a plurality of critical sections. Each of the flag bits indicates whether or not the corresponding critical section is available. In order to assure the mutual exclusion control, a flag bit access control register is provided which generates a plurality of control bits that are respectively assigned to the plurality of flag bits. The control bit is used to prevent two processors from using an identical critical section. A controller is provided so as to adequately control the above-mentioned registers.

Method and circuit for detecting overflow in operand multiplication

Abstract: Disclosed is a method and circuit for detecting overflow when multiplying operands. The disclosed method and circuit is configured to operate in parallel with a multiplier configured to multiply first and second n bit operands. In general, the multiplier circuit generates result operand which represents a multiplication of the first and second n bit operands. An overflow detection circuit is coupled to the multiplier circuit and configured to generate an overflow signal which indicates that the multiplication of the first and second n bit operands results in an overflow condition. The multiplier circuit comprises a compression circuit configured to generate the first and second 2n bit partial product operands as a function of the first and second n bit operands. An addition of the first and second 2n bit partial product operands produces the result operand. The multiplier circuit also includes a carry generation circuit configured to generate at least one carry bit representing a carry value of adding the (n-1) least significant bits of the first and second 2n bit partial product operands. The carry bit along with the most significant (n+1) bits of the first and second 2n bit partial product operands are provided to the overflow detection circuit. In response, the overflow detection circuit is configured to generate the overflow signal as a function of the carry bit and the most significant (n+1) bits of the first and second 2n bit partial product operands.

Multiplier carry bit compression apparatus and method

Abstract: A multiplier carry bit compression apparatus and method for a multiplier using Wallace tree addition structures uses a plurality of early and late carry bit compression operations for each level of the Wallace tree addition structure. For each level in a Wallace tree addition structure, each early carry bit compression operation compresses early compression bits prior to each corresponding late carry bit compression operation that compresses late carry bits.

Zero result prediction

Abstract: A zero result detector for detecting a zero result in the sum of a first operand A, a second operand B and a carry bit Cin operates by calculating {overscore (A)} and {overscore (A)}+1 and then comparing one of these with B (Cin=O, {overscore (A)}; Cin=1, {overscore (A)}+1) in dependence upon Cin. If the comparison shows equality, then the zero detect result Z is true.

Random number generator using lehmer algorithm

Abstract: A random number generator is provided that includes a plurality of bit generators for generating a first to last (e.g., 0'th to 30th) sum bits, a carry bit conversion section that receives a plurality of final output carries from a final bit generator of the plurality of bit generators and converts the received value to a prescribed-bit (e.g., 3-bit) signal, and a random number generation section adding the prescribed-bit signal outputted from the carry bit conversion section to the plurality of sum bits generated from the bit generation section to generate a random number. The random number generator is generated, for example, by adding a final output carry to a final sum generated from respective 31 bit generators to prevent wrap-around application of output carries of the final (e.g., 30th) a first bit generator to a 0'th bit generator.

High speed empty flag generator

Abstract: The present invention relates to a high speed empty flag generator and a method of generating a high speed empty flag which are achieved by generating a pre-empty flag in a clock ahead of a read address which is identical to a write address and by generating an empty flag as soon as a read address identical to the write address is generated after an elapse of one clock. The present invention includes a subtracter generating upper N-1 bits of a value resulted from subtracting 1 from a write address of N bits, a pre-empty flag generator generating an pre-empty flag when an output of upper N-1 bits of a rear address of N bits and an output of N-1 bits of the subtracter coincide by comparison, and a main empty flag receiving said pre-empty flag wherein the main empty flag generator generating an empty flag at a generating point of a first read signal after the pre-empty flag.

Sign extension circuit and method for unsigned multiplication and accumulation

Abstract: A carry save multiplier receives two input values having respective bit lengths A and B and provides sum and carry values, each having bit lengths A+B+1. A carry prediction circuit receives the most significant bit of the sum and carry values and provides an extension bit to be merged with less significant bits of the sum and carry bits. A carry save adder receives the altered sum and carry values, as well as a third input value to provide second sum and carry values. The second sum and carry values are added in a carry propagate adder to form a resulting value. This allows for a faster multiplication to form a product, and the faster addition of this product to another value such as an accumulator value.

Multi-instruction set flag preservation apparatus and method

Abstract: A method and apparatus for processing program instructions, utilizes native fixed length instructions that include at least one flag modification enable bit. The flag modification enable bit is typically sent with the operation code and other information in the native instruction and is set to allow updating of one or more flags, such as stored in flag registers, associated with non-native instructions, such as variable length instructions. In addition, a flag modification enable bit may be set to preserve flag bit setting for variable length instructions that are emulated using the fixed length native instructions, to prevent overwriting of flag settings during emulation of variable length instructions.

Multi-level carry-skip adder

Abstract: Circuits for binary adders to efficiently skip a carry bit over two or more bit positions with two or more carry-skip paths In one implementation, such a binary adder includes a network of carry-processing cells for producing kill, generate, and propagate signals and carry-skip cells for bypassing certain bit positions with dual-wire differential signal paths to provide high-speed processing of adding operations