Showing papers on "Carry flag published in 2006"

Digital signal processing circuit having a SIMD circuit

Abstract: An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.

Processor having a micro tag array that reduces data cache access power, and applicatons thereof

Abstract: Processors and systems having a micro tag array that reduces data cache access power. The processors and systems include a cache that has a plurality of datarams, a processor pipeline register, and a micro tag array. The micro tag array is coupled to the cache and the processor pipeline register. The micro tag array stores base address data bits or base register data bits, offset data bits, a carry bit, and way selection data bits. When a LOAD or a STORE instruction is fetched, at least a portion of the base address and at least a portion of the offset of the instruction are compared to data stored in the micro tag array. If a micro tag array hit occurs, the micro tag array generates a cache dataram enable signal. This signal enables only a single dataram of the cache.

Methods for reducing data cache access power in a processor using way selection bits

Abstract: Methods for reducing data cache access power in a processor. In an embodiment, a micro tag array is used to store base address or base register data bits, offset data bits, a carry bit, and way selection data bits associated with cache accesses. When a LOAD or a STORE instruction is fetched, at least a portion of the base address and at least a portion of the offset of the instruction are compared to data stored in the micro tag array. If a micro tag array hit occurs, the micro tag array generates a cache dataram enable signal. This signal activates only the cache dataram that stores the needed data.

3:2 Bit compressor circuit and method

Abstract: A circuit to convert three input bits (A, B and C) to a redundant format may include a first block with at least one transmission gate, and a second block with at least one static mirror. The first block may receive the three bits and output a sum bit, and the second block may receive the three bits and output a carry bit.

Micro tag array having way selection bits for reducing data cache access power

Abstract: Processors and systems having a micro tag array that reduces data cache access power. The processors and systems include a cache that has a plurality of datarams, a processor pipeline register, and a micro tag array. The micro tag array is coupled to the cache and the processor pipeline register. The micro tag array stores base address data bits or base register data bits, offset data bits, a carry bit, and way selection data bits. When a LOAD or a STORE instruction is fetched, at least a portion of the base address and at least a portion of the offset of the instruction are compared to data stored in the micro tag array. If a micro tag array hit occurs, the micro tag array generates a cache dataram enable signal. This signal enables only a single dataram of the cache.

Synthesis of area-efficient subtractor and divider functional blocks

Abstract: In one embodiment of the invention, a method of designing an integrated circuit including a subtraction arithmetic function is provided. The method includes generating a netlist of an area-efficient subtractor to subtract a first input vector from a second input vector. A netlist of a plurality of reduced full subtractor cells is generated with each including an exclusive-NOR gate evaluating a shared Boolean expression to generate a sum bit output and a carry bit output. The netlist of the reduced full subtractor cell is replicated for all bits of the area-efficient subtractor but for the least significant bit. One of a plurality of netlists of subtractor cells is selected for the least significant bit of the area-efficient subtractor in response to a flex bit.