Showing papers on "Carry flag published in 2017"

High Speed Error Tolerant Adder for Multimedia Applications

Abstract: In this paper, a 1-bit modified full adder (MFA) cell is proposed. This eliminates the carry propagation during the addition by allowing errors in the carry bit. Using the proposed MFA, a 16-bit high speed error tolerant adder (HSETA) circuit is designed with conventional carry select adder (CSLA) structure for higher order bits and MFA based structure for lower order bits. The performance of HSETA is compared with existing adders in terms of accuracy, gate count, delay and power dissipation. The gate count of the HSETA is reduced by 23% and speed is improved by 43% compared to a conventional 16-bit adder structure. Further, implementation on FPGA Spartan 6 shows that HSETA uses 53% fewer LUT and 63% fewer slices compared to the conventional adder. Image blending application is used to evaluate the performance of the HSETA. In addition, to perform extensive error analysis, an analytical model is developed for HSETA and tested for varying bit widths and input probabilities. The analytical model is validated through simulation.

Fast Prefix Adders for Non-uniform Input Arrival Times

Abstract: We consider the problem of constructing fast and small parallel prefix adders for non-uniform input arrival times. In modern computer chips, adders with up to hundreds of inputs occur frequently, and they are often embedded into more complex circuits, e.g. multipliers, leading to instance-specific non-uniform input arrival times. Most previous results are based on representing binary carry-propagate adders as parallel prefix graphs, in which pairs of generate and propagate signals are combined using complex gates called prefix gates. Examples of commonly-used adders are constructed based on the Kogge---Stone or Ladner---Fischer prefix graphs. Adders constructed in this model usually minimize the delay in terms of these prefix gates. However, the delay in terms of logic gates can be worse by a factor of two. In contrast, we aim to minimize the delay of the underlying logic circuit directly. We prove a lower bound on the delay of a carry bit computation achievable by any prefix carry bit circuit and develop an algorithm that computes a prefix carry bit circuit with optimum delay up to a small additive constant. Our algorithm improves the running time of a previous dynamic program for constructing a prefix carry bit from $$\mathcal {O}(n^3)$$O(n3) to $$\mathcal {O}(n \log ^2 n)$$O(nlog2n) while simultaneously improving the delay and size guarantee, where n is the number of bits in the summands. Furthermore, we use this algorithm as a subroutine to compute a full adder in near-linear time, reducing the delay approximation factor of 2 from previous approaches to 1.441 for our algorithm.

Design and Implementation of Power Efficient Modified Russian Peasant Multiplier using Ripple Carry Adder

Abstract: FIR filters, microprocessor and digital signal processor are the core system of multipliers. MAC is the most important building block in DSP system. The key element of high throughput multiplier and accumulator unit (MAC) is to achieve a high-performance digital signal processing application. In this paper, Modified Russian Peasant Multiplier (MRPM) using Ripple Carry Adder (RCA) has been proposed. According to Russian Rule‟s, Divide and conquer technique is used in the multiplication process. But, in perspective of digital design, only shifters and adders are used in Russian Peasant Multiplier to produce Partial Product Generation (PPG). A ripple carry adder is a logic circuit in which the carry-out of each full adder is the carry in of the next most significant full adder. It is called a ripple carry adder because each carry bit gets rippled into the next stage. Here, ripple carry adder is used for low power application. Reducing the chip size, increasing the speed and reducing the power consumption are main crucial factors in VLSI System design environment. The goal of this research work is to design the VLSI implementation of MAC for high-speed DSP applications. For designing the Multiplication and accumulation unit, different kinds of multipliers and adders are considered in this paper. The total operation is coded with Verilog HDL using ModelSim 6.3C, synthesized by using Xilinx ISE 12.4i design tool.

An efficient architecture for carry select adder

Abstract: Purpose Adders play a vital role in almost all digital designs, as all four arithmetic operations can be confined within addition. Hence, area and power optimization of the adders will result in overall circuit optimization. Being the fastest adder, the carry select adder (CSLA) gains higher importance among the different adder styles. However, it suffers from the drawback of increased power and area. The implementation of CSLA in digital circuits requires lots of study for optimization. Hence, to overcome this problem, various improvements were made to the CSLA structure to reduce area and, consequently, reduce power. Among these, modified CSLAs show a significant improvement, as they utilize a binary excess-1 code (BEC) to replace the add-one circuit. Design/methodology/approach This paper presents further enhancement in the modified CSLA by proposing a decision-based CSLA, which activates BEC on demand. This leads to reduced switching activity. The performance of the proposal is done by analyzing and comparing it with different adders. The comparison is done on the basis of three performance parameters: area, speed and power consumption. This is done by implementing the architecture on Xilinx Virtex5 XC5VLX30 in Verilog environment and is synthesized using Cadence® RTL Compiler® using TSMC 180-nm CMOS cell library. Findings Optimization of power, area and increasing the speed of operation are the three main areas of research in very-large-scale integration (VLSI) design for portable devices. As adders are the most fundamental units for any VLSI design, optimization at the adder level has a huge impact on the overall circuit. The modified CSLA has a BEC which continuously switches irrespective of the previous carry bit generated. The unwanted switching results in excess power consumption while also introducing additional delay. Hence, the author has proposed a decider circuit to avoid this excess switching activity. This allows switching of the BEC only when a previous carry is generated. The modified CSLA is based on the ripple carry adder, while the decider-based CSLA utilizes a carry look-ahead adder. This makes a decider-based CSLA faster while utilizing less area and power consumption when compared to the modified CSLA. Originality/value The efficiency of the proposed decider-based CSLA has been verified using Cadence RTL Compiler using TSMC 180-nm CMOS cell library and has been found to have 17 per cent power and 11.57 per cent area optimization when compared to the modified CSLA, while maintaining operating frequency.

Design method of four-bit BCD code summator based on strand displacement

Abstract: The invention relates to the field of strand displacement, and discloses a design method of a four-bit BCD code summator based on DNA strand displacement In the design method, a thought of double rail logic is introduced, a monorail logic circuit comprising 17 alternative denial gates, 12 nor gates, 2 or gates and 1 and gate is simulated through a DNA strand and is converted into a double rail logic to be participate in a reaction The method ensures that reaction is more stable and efficient, and logic of consequence obtained is clearer and easy to understand From the view of experimental data and experimental results, the method not only can correctly process carry bit and overflow during operation, but also is high in efficiency and stable in result, and explains the design effectiveness of the summator

Determine the carry bit of carry-sum generated by unsigned MBE multiplier without final addition

Abstract: Unpredictable value of carry bit in the summation of carry-sum is an annoying issue preventing carry-sum from being applied to designs with sign extension. In this paper, we propose a methodology to determine the carry bit of the carry-sum form output generated by Booth encoded multiplier without final addition. We discover that this carry bit is a constant "1" in traditional unsigned Modified Booth Encoded (MBE) multiplier, which makes carry-sum form applicable to hierarchy multiplier. Detailed proofs and gate level verification of our discovery is given, and experimental results show more than 20% shorter delay and up to 36% improvement in area-time product compared with non-carry-sum designs.

System and method for efficient implementation of prime field arithmetic in ARM processors

Abstract: The present invention provides a method for performing Elliptic Curve Cryptography (ECC) on data, the ECC implemented on multiple arithmetic layers. By performing multi-precision multiplication by implementing product-scanning to process columns of intermediary results in order to obtain a multiplication result by computing unsigned multiplication of data, accumulating a result of the multiplication and preserving a generated carry flag such that propagation of the carry flag is delayed, the present invention improves performance.